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CYDC128B16

Document #: 001-01638 Rev. *H Page 6 of 29

Functional Description

The CYDC128B16 is a low power complementary metal oxide

semiconductor (CMOS) 4k, 8k,16k x 16, and 8/16k x 8 dual-port

static RAM. Arbitration schemes are included on the devices to

handle situations when multiple processors access the same

piece of data. Two ports are provided, permitting independent,

asynchronous access for reads and writes to any location in

memory. The devices can be used as standalone 16-bit dual-port

static RAMs or multiple devices can be combined in order to

function as a 32-bit or wider master/slave dual-port static RAM.

An M/S

pin is provided for implementing 32-bit or wider memory

applications without the need for separate master and slave

devices or additional discrete logic. Application areas include

interprocessor/multiprocessor designs, communications status

buffering, and dual-port video/graphics memory.

Each port has independent control pins: Chip Enable (CE

), Read

or Write Enable (R/W

), and Output Enable (OE). Two flags are

provided on each port (BUSY

and INT). BUSY signals that the

port is trying to access the same location currently being

accessed by the other port. The interrupt flag (INT

) permits

communication between ports or systems by means of a mail

box. The semaphores are used to pass a flag, or token, from one

port to the other to indicate that a shared resource is in use. The

semaphore logic is comprised of eight shared latches. Only one

side can control the latch (semaphore) at any time. Control of a

semaphore indicates that a shared resource is in use. An

automatic power down feature is controlled independently on

each port by a Chip Enable (CE

) pin.

The CYDC128B16 are available in 100-pin TQFP packages.

Power Supply

The core voltage (V

) can be 1.8 V, 2.5 V or 3.0 V, as long as

it is lower than or equal to the I/O voltage.

Each port can operate on independent I/O voltages. This is

determined by what is connected to the V

DDIOL

and V

DDIOR

pins.

The supported I/O standards are 1.8-V/2.5-V LVCMOS and

3.0-V LVTTL.

Write Operation

Data must be set up for a duration of t

before the rising edge

of R/W

to guarantee a valid write. A write operation is controlled

by either the R/W

pin (see Figure 6 on page 20) or the CE pin

(see Figure 7 on page 20). Required inputs for non-contention

operations are summarized in Table 1.

If a location is being written to by one port and the opposite port

attempts to read that location, a port-to-port flowthrough delay

must occur before the data is read on the output; otherwise the

data read is not deterministic. Data will be valid on the port t

DDD

after the data is presented on the other port.

Read Operation

When reading the device, the user must assert both the OE and

pins. Data will be available t

ACE

after CE or t

DOE

after OE is

asserted. If the user wishes to access a semaphore flag, then the

SEM

pin must be asserted instead of the CE pin, and OE must

also be asserted.

Interrupts

The upper two memory locations may be used for message

passing. The highest memory location (1FFF for the

CYDC128B16) is the mailbox for the right port and the second

highest memory location (1FFE for the CYDC128B16) is the

mailbox for the left port. When one port writes to the other port’s

mailbox, an interrupt is generated to the owner. The interrupt is

reset when the owner reads the contents of the mailbox. The

message is user-defined.

Each port can read the other port’s mailbox without resetting the

interrupt. The active state of the busy signal (to a port) prevents

the port from setting the interrupt to the winning port. Also, an

active busy to a port prevents that port from reading its own

mailbox and, thus, resetting the interrupt to it.

If an application does not require message passing, do not

connect the interrupt pin to the processor’s interrupt request

input pin. On power up, an initialization program should be run

and the interrupts for both ports must be read to reset them.

The operation of the interrupts and their interaction with Busy are

summarized in Table 2.

Busy

The CYDC128B16 provide on-chip arbitration to resolve

simultaneous memory location access (contention). If both ports’

CEs are asserted and an address match occurs within t

each other, the busy logic determines which port has access. If

is violated, one port will definitely gain permission to the

location, but it is not predictable which port gets that permission.

BUSY

will be asserted t

BLA

after an address match or t

BLC

after

is taken LOW.

Master/Slave

A M/S pin is provided to expand the word width by configuring

the device as either a master or a slave. The BUSY

output of the

master is connected to the BUSY

input of the slave. This will

allow the device to interface to a master device with no external

components. Writing to slave devices must be delayed until after

the BUSY

input has settled (t

BLC

or t

BLA

), otherwise, the slave

chip may begin a write cycle during a contention situation. When

tied HIGH, the M/S

pin allows the device to be used as a master

and, therefore, the BUSY

line is an output. BUSY can then be

used to send the arbitration outcome to a slave.

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