Cypress Semiconductor CYDC128B16 Bedienungsanleitung PDF herunterladen (Seite 7)

CYDC128B16

Document #: 001-01638 Rev. *H Page 7 of 29

Input Read Register

The Input Read Register (IRR) captures the status of two

external input devices that are connected to the Input Read pins.

The contents of the IRR read from address x0000 from either

port. During reads from the IRR, DQ0 and DQ1 are valid bits and

DQ<15:2> are don’t care. Writes to address x0000 are not

allowed from either port.

Address x0000 is not available for standard memory accesses

when SFEN

= V

. When SFEN = V

, address x0000 is available

for memory accesses.

The inputs will be 1.8-V/2.5-V LVCMOS or 3.0-V LVTTL,

depending on the core voltage supply (V

). Refer to Table 3 for

Input Read Register operation.

Output Drive Register

The Output Drive Register (ODR) determines the state of up to

five external binary state devices by providing a path to V

for

the external circuit. These outputs are Open Drain.

The five external devices can operate at different voltages

(1.5 V ≤ V

DDIO

≤ 3.5 V) but the combined current cannot exceed

40 mA (8 mA max for each external device). The status of the

ODR bits are set using standard write accesses from either port

to address x0001 with a “1” corresponding to on and “0” corre-

sponding to off.

The status of the ODR bits can be read with a standard read

access to address x0001. When SFEN

= V

, the ODR is active

and address x0001 is not available for memory accesses. When

SFEN

= V

, the ODR is inactive and address x0001 can be used

for standard accesses.

During reads and writes to ODR DQ<4:0> are valid and

DQ<15:5> are don’t care. Refer to Table 4 for Output Drive

Semaphore Operation

The CYDC128B16 provides eight semaphore latches that are

separate from the dual-port memory locations. Semaphores are

used to reserve resources that are shared between the two ports.

The state of the semaphore indicates that a resource is in use.

For example, if the left port wants to request a given resource, it

sets a latch by writing a zero to a semaphore location. The left

port then verifies its success in setting the latch by reading it.

After writing to the semaphore, SEM

or OE must be deasserted

for t

SOP

before attempting to read the semaphore. The

semaphore value will be available t

SWRD

+ t

DOE

after the rising

edge of the semaphore write. If the left port was successful

(reads a zero), it assumes control of the shared resource,

otherwise (reads a one) it assumes the right port has control and

continues to poll the semaphore. When the right side has relin-

quished control of the semaphore (by writing a one), the left side

succeeds in gaining control of the semaphore. If the left side no

longer requires the semaphore, a one is written to cancel its

request.

Semaphores are accessed by asserting SEM

LOW. The SEM

pin functions as a chip select for the semaphore latches (CE

must remain HIGH during SEM LOW). A

0–2

represents the

semaphore address. OE

and R/W are used in the same manner

as a normal memory access. When writing or reading a

semaphore, the other address pins have no effect.

When writing to the semaphore, only I/O

is used. If a zero is

written to the left port of an available semaphore, a one appears

at the same semaphore address on the right port. That

semaphore can now only be modified by the side showing zero

(the left port in this case). If the left port now relinquishes control

by writing a one to the semaphore, the semaphore will be set to

one for both sides. However, if the right port had requested the

semaphore (written a zero) while the left port had control, the

right port would immediately own the semaphore as soon as the

left port released it. Table 5 shows sample semaphore opera-

tions.

When reading a semaphore, all 16/8 data lines output the

semaphore value. The read value is latched in an output register

to prevent the semaphore from changing state during a write

from the other port. If both ports attempt to access the

semaphore within t

SPS

of each other, the semaphore will

definitely be obtained by one side or the other, but there is no

guarantee which side controls the semaphore. On power up,

both ports should write “1” to all eight semaphores.

[+] Feedback

1 2 3 4 5 6 7 8 9 10 11 12 ... 29 30

Kommentare zu diesen Handbüchern

Keine Kommentare

Cypress Semiconductor CYDC128B16 Bedienungsanleitung Seite 7

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Nein Cypress Semiconductor CYDC128B16