CY7C603xx
Document #: 38-16018 Rev. *D Page 22 of 29
AC Operational Amplifier Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V
and 0°C <
T
A
< 70°C, or 2.4V to 3.0V and 0°C < T
A
< 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and
are for design guidance only.
AC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V
and 0°C <
T
A
< 70°C, or 2.4V to 3.0V and 0°C < T
A
< 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and
are for design guidance only.
AC Digital Block Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V
and 0°C <
T
A
< 70°C, or 2.4V to 3.0V and 0°C < T
A
< 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and
are for design guidance only.
Table 21.AC Operational Amplifier Specifications
Parameter Description Min. Typ. Max. Unit Notes
T
COMP
Comparator Mode Response Time, 50 mV Overdrive 100
200
ns
ns
Vdd > 3.0V.
2.4V < Vcc <3.0V.
Table 22.AC Analog Mux Bus Specifications
Parameter Description Min. Typ. Max. Unit Notes
F
SW
Switch Rate – – 3.17 MHz
Table 23.3.3V AC Digital Block Specifications
Function Description Min. Typ. Max. Unit Notes
All Functions Maximum Block Clocking Frequency (< 3.6V) 24.6 MHz 3.0V < Vdd < 3.6V.
Timer/
Counter/
PWM
Enable Pulse Width 50
[12]
– – ns
Maximum Frequency – – 24.6 MHz
Dead Band Kill Pulse Width:
Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 50 – – ns
Disable Mode 50 – – ns
Maximum Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.
SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz
due to 2 x over clocking.
SPIS Maximum Input Clock Frequency – – 4.1 MHz
Width of SS_ Negated Between Transmissions 50 – – ns
Transmitter Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Receiver Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Note
12. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
(53 Seiten)
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