Cypress Semiconductor ISR 37000 CPLD Spezifikationen PDF herunterladen (Seite 18)

Design Considerations for ISR Programming of Cypress CPLDs

tion devices. For the F

LASH

370i it is permissible to actually let

the JTAGen pin float to retain the I/O capability of dual-mode

pins. For the Ultra37000 devices this pin must be driven to a

LOW level to ensure the I/O functionality. For Ultra37128 and

smaller devices a weak pull-down device replaces the bus-

hold latch on the JTAGen pin. This pull-down device (see the

data sheet parameter I

JTAG

, which shows the strength of the

pull-down device) keeps the pin in the LOW state after pro-

gramming and prevents the need for external biasing on the

JTAGen pin if a Ultra37000 device replaces a F

LASH

370i de-

vice. Early Ultra37256P160 silicon did not have this pull down

device on the JTAGen pin but more recent silicon has this

device. If the pull-down device is not employed then a bus-

hold latch is employed and this latch could hold a HIGH value

on the pin. With multiple devices in the chain, some devices

being Ultra37128 and smaller and some being

Ultra37256P160 early silicon or F

LASH

370i devices, it is still

possible for the JTAGen pin to be pulled into the HIGH state.

Two methods for driving the JTAGen pin LOW, using a exter-

nal pull-down resistor and using an external component are

presented.

Using a Pull-down Resistor to Drive the JTAGen Pin LOW

to Use the I/O Function of the Dual-Function Pins

The JTAGen pin can be held at a TTL LOW by using a pull-

down resistor to ground. This works fine provided there are

not too many devices in the ISR chain. The problem with the

simple resistor is that the bus-hold latches on the JTAGen

pins may disturb the pull-down operation if there are many

other F

LASH

370i devices in the chain. This is because the bus-

hold latches that are connected in parallel produce a lower

source impedance. The bus-hold latch differences between

the two ISR family members are discussed further in this note.

The resistor must be able to provide a low enough resistance

to overpower the combined bus-hold latches in parallel such

that the voltage on the JTAGen pin drops below the trip point

trip

) of the bus-hold latches. Once the JTAGen pin voltage

drops below V

trip

all the bus-hold latches connected in parallel

will flip to the desired LOW state. The maximum resistance

that is guaranteed to overpower N F

LASH

370i bus-hold latch-

es in parallel is given by the formula:

pulldown

= V

trip

/(N*(I

BHHO

))

where V

trip

is 1.5V and I

BHHO

is –500 µA (maximum current

that is guaranteed to invert the state of a single bus-hold

latch). R

pulldown

is 3 kΩ for 1 device, 600Ω for 5 devices, and

300Ω for 10 devices in the chain. It is recommended that the

number of devices in the chain be limited to 5 devices if the

other devices in the chain are all F

LASH

370i devices. The

above limitation of 5 devices in the chain is suggested be-

cause the resistor value would need to be reduced which

would place too high a DC current load on the JTAGen signal

driven to 12V from the ISR cable. With a pull-down resistance

of 600Ω, the DC current load on the JTAGen pin is 12/600 or

20 mA, which is an acceptable load. Resistor values less than

600Ω would require a higher wattage resistor than the stan-

dard 1/4 watt rating, assuming 12V is needed for program-

ming F

LASH

370i devices in the same chain. If only

Ultra37256P160 early silicon devices are in the chain and the

UltraISRPCCABLE is used then the JTAGen pin only goes to

a TTL HIGH so the number of devices in the chain can be

increased to 10. The above restriction of the pull-down resis-

tor can be avoided by using an external component to choose

between a TTL HIGH level and a TTL LOW level on the

JTAGen pin. Again the need for external biasing may not be

needed in many case because of the pull-down device incor-

porated on the Ultra37128 devices and smaller and to be in-

cluded on the Ultra37256 as well.

Using an External Component to Drive the JTAGen Pin

LOW to Use the I/O Function of the Dual-Function Pins

The JTAGen pin can be driven LOW using any of the solutions

already presented in Figure 14 regarding using the dual-

function pins in dual-function mode. The only difference is that

the JTAG input is JTAGen, which is tied to V

instead of one

of the four JTAG pins and the “signal” input is connected to

ground. You may be able to use unused resources in the ex-

ternal component solutions presented in Figure 14 to imple-

ment this logic. Any of these solutions can be used for multiple

Ultra37000 devices ganged together. Figure 22 shows two

examples for driving the JTAGen pin from the control of signal

ISR*. As mentioned before, a pull-up resistor is also needed

on the ISR* signal at the 10-pin header connector.

Figure 23 shows the JTAGen pin driven by an extra I/O pin of

the Ultra37000 device by simply inverting the ISR* control

signal. This would seem to be a simple alternative to adding

extra components. This solution, however, won’t work. The

problem is that the I/O pins of the device enter three-state

when the ISR mode is enabled (JTAGen driven HIGH). Be-

cause the I/O is three-stated there is no way to drive the

JTAGen pin LOW. The dual-function pins are stuck in the

JTAG function because the bus-hold latch, which is always

enabled, has latched a HIGH level on the pin. Figure 24

shows how to combine dual-function F

LASH

370i and

Ultra37000 devices in the same chain with the appropriate

JTAGen connections assuming the user wants to use one

dual-function pin in dual-function mode for each of the

Ultra37000 devices. The figure shows that one mux can be

used for two Ultra37000 devices but many more devices can

use the same mux output signal. In this example the TMS pin

on both Ultra37000 devices is used in dual-function mode

where the I/Os are used as JTAG pins and as input pins. The

Figure 22. JTAGen Driven for the Ultra37000

Ultra37000

JTAGen

ISR*

Ultra37000

5 volts

JTAGen

ISR*

1 2 ... 13 14 15 16 17 18 19 20

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