Cypress Semiconductor ISR 37000 CPLD Spezifikationen PDF herunterladen (Seite 19)

Design Considerations for ISR Programming of Cypress CPLDs

10-kΩ resistor on the ISR* signal is required to keep the mux

input HIGH when the ISR cable is removed from the board to

keep the JTAGen input LOW. Remember that, if it is not nec-

essary to use the dual-function pins in dual-function mode,

the mux can be removed and the JTAGen pin can be tied to

or left connected to the JTAGen pin from the 10-pin con-

nector.

At this point the user should understand how to connect

LASH

370i and or Ultra37000 devices in an ISR chain and

how to bias the ISR interface for his programming and func-

tional needs. There are some remaining minor functional dif-

ferences between the two device families related to the place-

ment of the bus-hold latches on the five JTAG interface pins,

which was addressed in the Device-Specific ISR Design Con-

siderations section of this application note.

Figure 23. JTAGen Incorrectly Driven by Ultra37000 I/O

ISR*

Ultra37000

JTAGen

Figure 24. Cascading Dual-Function Ultra37000 and F

LASH

370i Devices in the Same Chain

ISR Programming

Cable Connector

JTAGen

TDI

TDO

TCK

TMS

ISRen

TDI

TDO

TCK

TMS

CY7C375i-125AC

JTAGen

TDI

TDO

TCK

TMS

Ultra37128P160

JTAGen

TDI

TDO

TCK

TMS

Ultra37256P160

ISR*

10 kΩ

input1

input2

1 2 ... 14 15 16 17 18 19 20

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