Design Considerations for ISR Programming of Cypress CPLDs
7
divider effect between the source impedance of the buffer and
the characteristic impedance of the transmission line Z
O
. As
illustrated in the “bad layout” above, the long stubs and asso-
ciated impedance mismatches cause reflections at each
node. As the initial voltage wavefront propagates to the end
of the transmission line, reflections from adjacent nodes can
affect the voltage waveform at earlier receivers by creating
notching. If the notch resides near the trip point of the ISR
device, (1.5V for both Delta39K LVTTL levels and Ultra37000
devices), then it could result in a false-clock scenario resulting
in ISR operation failure. This effect more typically occurs with
multiple devices in the ISR chain because of differing clock
line trace lengths and improper trace layout.
The daisy chain set-up shown in the “bad layout” example of
Figure 8 is not recommended. With source termination, as
used in all ISR programming cables, all load devices should
be lumped at the end of the line. As this is not practical for
more than one ISR device, a buffering scheme must be adopt-
ed. A better layout practice is shown in the “good layout” ex-
ample, yet this layout may still be susceptible to ringing or
notching depending on the precise layout. Recall that since
all ISR programming cables employ series termination, an on-
board buffer is necessary. Other schemes for providing the
best signal integrity are described in detail below.
TCK Clock Layout
The layout of the clock shown in Figure 9 can make a big
difference in reducing the transmission line effect of notching.
If the clock trace is laid out exactly as shown in Figure 8, then
the first device can experience a notch of duration 2T, where
T is the transmission line delay from device #1 to the end of
the chain at device #5. Making the clock trace the same length
to device #1 as device #5, as shown in Figure 9, can remove
this notching effect. In general it is good to avoid stubs on the
clock line to minimize this effect.
While this scheme can be effective, its implementation on a
PCB may not be practical. This is due to the fact that the split
traces must be impedance matched to the feed wire in order
to prevent reflections and ringing between junctions.
An example implementation is shown in Figure 10. Here, the
split trace widths are scaled smaller such that the parallel
combination of the split traces matches with the characteristic
impedance of the feed trace. The example shows a clock tree
distributed to four ISR devices, each end terminated to a
proper Thevenin termination voltage. The characteristic im-
pedance of the feed wire, Z
O
, matches with the four thin
scaled 4*Z
O
traces in parallel. While this configuration results
in optimal signal integrity, it is little used on PCBs. This is due
Figure 8. Transmission Line Effect—Notching
ISR
#1
ISR
#5
ISR
#3
TCK Buffer
TCK Buffer
ISR
device
ISR
device
ISR
device
V
CC
BAD
Layout
GOOD
Layout
Improper termination for daisy-chain
Long stubs promote ringing, notching
R1
R2
Parallel termination at end of daisy-chain
Short stubs minimize impedance discontinuities and reflections
ISR
#2
ISR
#4
1.5V
Notching possible at
ISR device #1
ISR
device
ISR
device
Figure 9. Clock Trace Layout
PCB
#3
#4
Better clock
trace layout
#2
#1
#7
#8
#6
#5
with equal trace
lengths for each
ISR device to
prevent notching
(30 Seiten)
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