Cypress Semiconductor ISR 37000 CPLD Spezifikationen PDF herunterladen (Seite 6)

Design Considerations for ISR Programming of Cypress CPLDs

Board Layout Considerations

Transmission line effects are a critical design consideration to

ensure suitable signal integrity and reliable In-System Repro-

grammability performance.

Relevant design considerations discussed in this section in-

clude: key transmission line effects to minimize, recommend-

ed termination practices, signal layout, and on-board buffer-

ing guidance.

Condition for Terminating Transmission Line

Not all digital circuits require termination measures. For ISR

programming applications, however, transmission line effects

are most often significant. Transmission line effects take the

form of unwanted voltage reflections and ringing under cer-

tain conditions. These effects are caused by impedance mis-

match between source drivers, traces, receiver loads, and

any discontinuity between them. For instance, low-imped-

ance outputs driving high-impedance inputs will yield a cer-

tain reflection coefficient. The size of the voltage reflection is

directly proportional to the impedance mismatch at a particu-

lar node. These inadvertent reflections can interfere at device

receivers, thereby degrading system operation.

The classical way of stating the condition for a voltage reflec-

tion to occur is when the signal rise time is less than or equal

to the round-trip (two-way) propagation delay of the line. In

equation form, transmission line effects are prominent when:

Eq. 1

where L is the length of PCB trace, t

is the rise time of the

signal at the source, and t

pdL

is the one-way propagation de-

lay of the line per unit length.

It is important to note that transmission line effects depend on

signal rise and fall times rather then on signaling rate. For the

Cypress ISR programming cables, for example, even though

each clock cycle can span several hundred nanoseconds, the

signal transition edge rates of the cable drivers are fast, in the

order of 5 to 10 ns. Likewise, typical CPLD rise/fall times are

on the order of a few nanoseconds. Transmission line effects

are therefore inevitable; however, certain layout practices can

greatly reduce their harmful effects.

These effects can occur on any of the four ISR signals but are

of special concern for the clock signal TCK. This is because

there is potentially plenty of time, many hundreds of nanosec-

onds, for the data signals to settle before the next rising clock

edge. Further, the electrical characteristics of these other sig-

nals are critical only at the active edge of TCK. Particular care

should be taken with the clock signal trace layout.

Thus, even for relatively short trace lengths, transmission line

effects can be prominent at fast edge rates. A discussion of

transmission line effects is necessary to understand how to

best design the ISR chain. This discussion also applies to any

method of ISR programming occurring at higher frequency,

such as by an on-board microprocessor. Additional details

can be found in the references located at the end of this ap-

plication note.

Transmission Line Effects

There are two significant transmission line effects that can be

encountered. They are illustrated in Figure 7 and Figure 8.

These effects are overshoots with ringing after the edge tran-

sition and notching of the signal during the edge transition

itself.

The first effect, overshooting and ringing, is worst-case with

very light capacitive load. Severe signal bounce can cross the

receiver’s input threshold, thereby causing false-clocking.

While the ringing is not typically big enough to cause failure,

it can be minimized by observing proper termination tech-

niques.

The recommended interconnect scheme for a single load

connected to an ISR header is shown in Figure 7. In the “bad

layout” example, an external buffer drives a long transmission

line with no termination used. The impedance mismatch from

cable to PCB trace, combined with the lack of termination,

creates voltage reflections and ringing. In the “good layout”

example, as implemented by any Cypress ISR programming

cable, source termination acts to absorb reflections. Placing

the CPLD close to the ISR header will minimize the effect of

the impedance mismatch between the ribbon cable and the

device. Source termination is already employed in the cable,

so no other termination components are necessary.

Since all ISR programming cables use source termination to

absorb voltage reflections from the line, any additional type of

end termination is not recommended

The effect of a single

load pull-down resistor would degrade the V

output high

level due to the voltage divider effect of the termination resis-

tor and the buffer plus R

resistance. A parallel termination

load, which employs a resistor connection to V

and to

ground, would degrade the V

of the output buffer due to the

voltage divider action of the resistor to V

and the buffer plus

resistance to ground.

The other transmission line effect that can cause false-clock-

ing is a notching, or glitching, of the clock transition while in

the middle of the transition itself. The notch is evident on both

edges of the clock. The notch occurs because of a voltage

pdL

•

-------------------

≥

Figure 7. Transmission Line Effect—Ringing

ISR

device

Cable Buffer

PCB

Ribbon Cable

Z=100

Ω

ISR

device

PCB

ISR Header

placed close to receiver

1.5V

Ringing with light capacitive load

causing false-clocking

BAD

Layout

Lack of termination

Large impedance mismatch from cable to trace

GOOD

Layout

Source termination absorbs voltage reflections

Impedance discontinuity is minimized

Ribbon Cable

Z=100

Ω

Large impedance

mismatch

1 2 3 4 5 6 7 8 9 10 11 ... 19 20

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