Cypress Semiconductor CYV15G0404DXB Betriebsanweisung Seite 1

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised October 4, 2004CYV15G0404DXB Evaluation Board

CYV15G0404DXB Evaluation BoardUsers Guide Page 10 of 565.0 Board Photograph and Pin DescriptionsFigure 5-1 shows the different connectors and pins

CYV15G0404DXB Evaluation BoardUsers Guide Page 11 of 56Figure 5-2 shows the parallel I/O and reference clock connectors for channel A. Channels B, C

CYV15G0404DXB Evaluation BoardUsers Guide Page 12 of 56J12x REFCLKx- SMA Connector for REFCLKx -• Negative input of reference clock for channel xJ13

CYV15G0404DXB Evaluation BoardUsers Guide Page 13 of 56Figure 5-3 shows the optical interface connector J25, along with the signal name for each pin

CYV15G0404DXB Evaluation BoardUsers Guide Page 14 of 56 Table 5-3 provides a brief description of the control latches for the configuration interfac

CYV15G0404DXB Evaluation BoardUsers Guide Page 15 of 56RXCKSELx Receive Clock Select • When 1, the associated Output Registers are clocked by REFCLK

CYV15G0404DXB Evaluation BoardUsers Guide Page 16 of 56Table 5-4 shows the mapping of latches in the device. Each row of the table is defined by an

CYV15G0404DXB Evaluation BoardUsers Guide Page 17 of 566.0 Adjusting Settings on the BoardTo successfully operate the device, the SPDSELx settings

CYV15G0404DXB Evaluation BoardUsers Guide Page 18 of 56 6.4 Reference Clock Input OptionsThe reference clock signal, REFCLKx, can have three differe

CYV15G0404DXB Evaluation BoardUsers Guide Page 19 of 567.0 Test ModesThe different test modes discussed in this document are BIST, parallel data, a

CYV15G0404DXB Evaluation BoardUsers Guide Page 2 of 56TABLE OF CONTENTS1.0 OVERVIEW ...

CYV15G0404DXB Evaluation BoardUsers Guide Page 20 of 56Cables needed:• SMA to SMA coaxial cables• Power supply cables (banana plug cables).7.1.1.2 T

CYV15G0404DXB Evaluation BoardUsers Guide Page 21 of 56 Steps 10 through 12 are for result verification of the BIST on channel A:10.Verify that the

CYV15G0404DXB Evaluation BoardUsers Guide Page 22 of 56Optical TransmissionFor external loopback with an optical signal, connect an optical module i

CYV15G0404DXB Evaluation BoardUsers Guide Page 23 of 561. Ensure that there are no SMA cables connected to the REFCLKx inputs. Make sure the oscilla

CYV15G0404DXB Evaluation BoardUsers Guide Page 24 of 56Cables needed:• Two SMA-to-SMA coaxial cables• Power supply cables• DG2020 cables with approp

CYV15G0404DXB Evaluation BoardUsers Guide Page 25 of 56the “MORE” button to customize your clock's settings. Your clock definition needs to be

CYV15G0404DXB Evaluation BoardUsers Guide Page 26 of 56Note. The output of the DG2020 for this PDA file are mapped to POD-A bits 0–11. If outputs ne

CYV15G0404DXB Evaluation BoardUsers Guide Page 27 of 56 The following steps are done for result verification on channels C and D:1. For channel C, a

CYV15G0404DXB Evaluation BoardUsers Guide Page 28 of 567.3.2 Test Equipment Set-upFigure 7-2 shows the test equipment set-up for BIST on channel A a

CYV15G0404DXB Evaluation BoardUsers Guide Page 29 of 56 Steps 10 through 12 are for result verification of the BIST on channel A:11.Verify that the

CYV15G0404DXB Evaluation BoardUsers Guide Page 3 of 56LIST OF FIGURESFigure 4-1. CYV15G0404DXB Block Diagram ...

CYV15G0404DXB Evaluation BoardUsers Guide Page 30 of 56Appendix A: Schematic Diagram of CYV15G0404DXB Evaluation Board[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 31 of 56Figure A-1. CYV15G0404DXB Eval Board Top-level Schematic Ch. A[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 32 of 56Figure A-2. CYV15G0404DXB Eval Board Top-level Schematic Ch. B[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 33 of 56Figure A-3. CYV15G0404DXB Eval Board Top-level Schematic Ch. C[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 34 of 56Figure A-4. CYV15G0404DXB Eval Board Top-level Schematic Ch. D[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 35 of 56Figure A-5. CYV15G0404DXB Eval Board Optical Schematic[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 36 of 56Figure A-6. CYV15G0404DXB Eval Board Control Signal Schematic[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 37 of 56Figure A-7. CYV15G0404DXB Eval Board Input Power Schematic[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 38 of 56Appendix B: PCB Layout for CYV15G0404DXB Evaluation Board[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 39 of 56Figure B-1. CYV15G0404DXB Evaluation Board Fabrication Drawing[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 4 of 56LIST OF TABLESTable 5-1. Description of Connectors of the CYV15G0404DXB Evaluation Board ...

CYV15G0404DXB Evaluation BoardUsers Guide Page 40 of 56Figure B-2. CYV15G0404DXB Evaluation Board Assembly Drawing[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 41 of 56Figure B-3. CYV15G0404DXB Eval Board Top Silk Layer[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 42 of 56Figure B-4. CYV15G0404DXB Eval Board Top Pastemask Layer[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 43 of 56Figure B-5. CYV15G0404DXB Eval Board Top Solder Mask Layer[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 44 of 56Figure B-6. CYV15G0404DXB Eval Board Top Layer[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 45 of 56Figure B-7. CYV15G0404DXB Eval Board Ground Plane Layout[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 46 of 56Figure B-8. CYV15G0404DXB Eval Board First Internal Layer[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 47 of 56Figure B-9. CYV15G0404DXB Eval Board Device Power Layer Layout[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 48 of 56Figure B-10. CYV15G0404DXB Eval Board Second Internal Layer Layout[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 49 of 56Figure B-11. CYV15G0404DXB Eval Board Power Layout[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 5 of 561.0 OverviewThe CYV15G0404DXB Quad Independent-Channel HOTLink II™ Transceiver is a point-to-

CYV15G0404DXB Evaluation BoardUsers Guide Page 50 of 56Figure B-12. CYV15G0404DXB Eval Board Third Internal Layer Layout[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 51 of 56Figure B-13. CYV15G0404DXB Eval Board Bottom Layer Layout[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 52 of 56Figure B-14. CYV15G0404DXB Eval Board Bottom Solder Mask Layer Layout[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 53 of 56Figure B-15. CYV15G0404DXB Eval Board Bottom Pastemask Layer Layout[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 54 of 56Figure B-16. CYV15G0404DXB Eval Board Bottom Silkscreen Layout[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 55 of 56Appendix C: Bill Of Material (BOM) CYV15G0404DXB Evaluation Board[+] Feedback

CYV15G0404DXB Evaluation BoardUsers Guide Page 56 of 56© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to ch

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CYV15G0404DXB Evaluation BoardUsers Guide Page 6 of 56• Compatible with— Fiber-optic modules— Copper cables— Circuit board traces• Per-channel Link

CYV15G0404DXB Evaluation BoardUsers Guide Page 7 of 56Figure 4-2 shows the transmitter section of CYV15G0404DXB in more detail. The building blocks

CYV15G0404DXB Evaluation BoardUsers Guide Page 8 of 56Figure 4-3 shows the receive section of the CYV15G0404DXB. The serial data input passes throug

CYV15G0404DXB Evaluation BoardUsers Guide Page 9 of 56Figure 4-4 shows the device configuration and control block diagram. The inputs are the extern