Cypress Semiconductor CYV15G0404DXB Betriebsanweisung PDF herunterladen (Seite 5)

CYV15G0404DXB Evaluation Board

Users Guide

Page 5 of 56

1.0 Overview

The CYV15G0404DXB Quad Independent-Channel HOTLink II™ Transceiver is a point-to-point or point-to-multipoint communi-

cations building block that allows the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper

transmission lines) at signaling speeds ranging from 195–1500 MBaud per serial link. The independence of each channel

provides the ability to simultaneously transport different types of data at different signaling rates across multiple channels.

This user’s guide describes the operation and interface of the CYV15G0404DXB evaluation board. The evaluation board allows

users to become familiar with the functionality of the CYV15G0404DXB.

2.0 Kit Contents

• CYV15G0404DXB-EVAL (the evaluation board)

• Dear Customer letter

• A CD containing

— CYV15G0404DXB data sheet

— CYV15G0404DXB Evaluation Board User’s Guide

— CYV15G0404DXB application notes

— 0404EN.PDA and 0404BYP.PDA files for the DG2020 parallel data generator

— BSDL model

3.0 Features of the CYV15G0404DXB

• Quad channel transceiver for 195- to 1500-MBaud serial signaling rate

— Aggregate throughput of up to 12 Gbits/second

• Second-generation HOTLink

technology

• Compliant with multiple standards

— ESCON

, DVB-ASI, SMPTE 292M, SMPTE 259M, Fibre Channel and Gigabit Ethernet (GbE) (IEEE802.3z)

— 8B/10B coded data or 10 bit uncoded data

• Truly independent channels

— Each channel can perform reclocker function

— Each channel can operate at a different signaling rate

— Each channel can transport a different type of data

• Selectable input/output clocking options

• Internal phase-locked loops (PLLs) with no external PLL components

• Selectable differential PECL-compatible serial inputs per channel

— Internal DC-restoration

• Redundant differential PECL-compatible serial outputs per channel

— Source matched for 50Ω transmission lines

— No external bias resistors required

— Signaling-rate controlled edge-rates

• MultiFrame™ Receive Framer provides alignment options

— Bit and byte alignment

— Comma or Full K28.5 detect

— Single or Multi-byte Framer for byte alignment

— Low-latency option

• Synchronous LVTTL parallel interface

• JTAG boundary scan

• Built-In Self-Test (BIST) for at-speed link testing

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