Cypress Semiconductor CYV15G0404DXB Betriebsanweisung PDF herunterladen (Seite 6)

CYV15G0404DXB Evaluation Board

Users Guide

Page 6 of 56

• Compatible with

— Fiber-optic modules

— Copper cables

— Circuit board traces

• Per-channel Link Quality Indicator

— Analog signal detect

— Digital signal detect

• Low-power 3W @ 3.3V typical

• Single 3.3V supply

• 256-ball thermally enhanced BGA

• 0.25µ BiCMOS technology

4.0 Functional Description of CYV15G0404DXB

Figure 4-1 shows the block diagram of CYV15G0404DXB, which has four pairs of transmit and receive channels (A,B,C,D). Each

of the four modules represents a transceiver channel. The left side of the transceiver represents the transmitter, which is

composed of a phase-align buffer, 8B/10B encoder and serializer. The right side of the transceiver is the receiver, which is

composed of a deserializer, framer, 8B/10B decoder and elasticity buffer.

CYV15G0404DXB Transceiver Logic Block Diagram

x10

Serializer

Phase

Encoder

8B/10B

Decoder

8B/10B

x11

Framer

Deserializer

x10

Serializer

Encoder

8B/10B

Decoder

8B/10B

x11

Framer

Deserializer

x10

Serializer

Encoder

8B/10B

Decoder

8B/10B

x11

Framer

Deserializer

x10

Serializer

Encoder

8B/10B

Decoder

8B/10B

x11

Framer

Deserializer

TXDA[7:0]

RXDA[7:0]

TXDB[7:0]

RXDB[7:0]

TXDC[7:0]

RXDC[7:0]

TXDD[7:0]

RXDD[7:0]

OUTA1

OUTA2

INA1

INA2

OUTB1

OUTB2

INB1

INB2

OUTC1

OUTC2

INC1

INC2

OUTD1

OUTD2

IND1

IND2

Align

Buffer

Phase

Align

Buffer

Phase

Align

Buffer

Phase

Align

Buffer

Elasticity

Buffer

Elasticity

Buffer

Elasticity

Buffer

Elasticity

Buffer

TXCTA[1:0]

RXSTA[2:0]

TXCTB[1:0]

RXSTB[2:0]

TXCTC[1:0]

RXSTC[2:0]

TXCTD[1:0]

RXSTD[2:0]

REFCLKA±

REFCLKB±

REFCLKC±

REFCLKD±

Figure 4-1. CYV15G0404DXB Block Diagram

[+] Feedback

1 2 3 4 5 6 7 8 9 10 11 ... 56 57

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