Document Number: 001-53754 Rev. *F Page 8 of 50
Pinouts
The automotive CY8C24x94 PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of digital I/O. However, V
SS
, V
DD
, and XRES are not capable of digital I/O.
56-Pin Part Pinout (with XRES pin)
Table 2. 56-Pin Part Pinout (QFN)
Pin
No.
Type
Name Description
Figure 3. CY8C24894 56-Pin PSoC Device
Digital Analog
1 I/O I, M P2[3] Direct switched capacitor block input
2 I/O I, M P2[1] Direct switched capacitor block input
3 I/O M P4[7]
4 I/O M P4[5]
5 I/O M P4[3]
6 I/O M P4[1]
7 I/O M P3[7]
8 I/O M P3[5]
9 I/O M P3[3]
10 I/O M P3[1]
11 I/O M P5[7]
12 I/O M P5[5]
13 I/O M P5[3]
14 I/O M P5[1]
15 I/O M P1[7] I
2
C serial clock (SCL)
16 I/O M P1[5] I
2
C serial data (SDA)
17 I/O M P1[3]
18 I/O M P1[1] I
2
C SCL, ISSP SCLK
[4]
19 Power V
SS
Ground connection
20 DNC Do not connect anything to this pin
21 DNC Do not connect anything to this pin
22 Power V
DD
Supply voltage
23 I/O P7[7]
24 I/O P7[0]
25 I/O M P1[0] I
2
C SDA, ISSP SDATA
[4]
26 I/O M P1[2]
27 I/O M P1[4] Optional external clock (EXTCLK) input
28 I/O M P1[6]
29 I/O M P5[0]
30 I/O M P5[2]
Pin
No.
Type Name Description
31 I/O M P5[4]
Digital Analog
32 I/O M P5[6] 45 I/O I, M P0[0] Analog column mux input
33 I/O M P3[0] 46 I/O I, M P0[2] Analog column mux input
34 I/O M P3[2] 47 I/O I, M P0[4] Analog column mux input
35 I/O M P3[4] 48 I/O I, M P0[6] Analog column mux input
36 Input XRES Active high external reset with internal
pull-down
49 Power V
DD
Supply voltage
37 I/O M P4[0] 50 Power V
SS
Ground connection
38 I/O M P4[2] 51 I/O I, M P0[7] Analog column mux input
39 I/O M P4[4] 52 I/O I/O, M P0[5] Analog column mux input and column output
40 I/O M P4[6] 53 I/O I/O, M P0[3] Analog column mux input and column output
41 I/O I, M P2[0] Direct switched capacitor block input 54 I/O I, M P0[1] Analog column mux input
42 I/O I, M P2[2] Direct switched capacitor block input 55 I/O M P2[7]
43 I/O M P2[4] External analog ground (AGND) input 56 I/O MP2[5]
44 I/O M P2[6] External voltage reference (VREF) input EP Power V
SS
Exposed pad is not connected internally. Connect
to circuit ground for best performance
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Note
4. These are the ISSP pins, which are not high Z when coming out of reset state. See the PSoC Technical Reference Manual for details.
AI, M, P2[3]
AI, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
M, P1[3]
I2C SCL, M, P1[1]
V
SS
DNC
V
DD
P7[7]
P7[0]
I2C SDA, M, P1[0]
M, P1[2]
EXTCLK, M, P1[4]
M, P1[6] P2[4], M, Ext. AGND
P2[6], M, Ext. VRef
P0[0], M, AI
P0[2], M, AI
P0[4], M, AI
P0[6], M, AI
V
DD
V
SS
P0[7], M, AI
P0[5], M, AIO
P0[3], M, AIO
P0[1], M, AI
P2[7], M
P2[5], M56
P2[2], AI, M
P2[0], AI, M
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DNC
QFN
(Top View)
(21 Seiten)
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