Cypress Semiconductor Perform CY7C1513KV18 Bedienungsanleitung PDF herunterladen (Seite 12)

CYWUSB6934

CYWUSB6932

Document Number : 38-16007 Rev. *L Page 12 of 34

3 Underflow A The Underflow A bit is used to enable the interrupt associated with an underflow condition with the Receive

SERDES Data A register (Reg 0x09)

1 = Underflow A interrupt enabled for Receive SERDES Data A

0 = Underflow A interrupt disabled for Receive SERDES Data A

An underflow condition occurs when attempting to read the Receive SERDES Data A register (Reg 0x09) when

it is empty.

2 Overflow A The Overflow A bit is used to enable the interrupt associated with an overflow condition with the Receive

SERDES Data A register (0x09)

1 = Overflow A interrupt enabled for Receive SERDES Data A

0 = Overflow A interrupt disabled for Receive SERDES Data A

An overflow condition occurs when new receive data is written into the Receive SERDES Data A register (Reg

0x09) before the prior data is read out.

1 EOF A The End of Frame A bit is used to enable the interrupt associated with an End of Frame condition with the Channel

A Receiver.

1 = EOF A interrupt enabled for Channel A Receiver.

0 = EOF A interrupt disabled for Channel A Receiver.

The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit

has been detected, and then the number of invalid bits in a frame exceeds the number in the EOF length field.

If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared

by reading the receive status register.

0 Full A The Full A bit is used to enable the interrupt associated with the Receive SERDES Data A register (0x09) having

data written into it.

1 = Full A interrupt enabled for Receive SERDES Data A

0 = Full A interrupt disabled for Receive SERDES Data A

A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data

A register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether

or not a complete byte has been received.

Bit Name Description

Note

5. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The

status bits are affected by TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the receive status will read 0 if the IC is not in receive mode. These registers

are read-only.

Table 10. Receive SERDES Interrupt Status

[5]

Addr: 0x08 REG_RX_INT_STAT Default: 0x00

76543210

Valid B Flow Violation

EOF B Full B Valid A Flow Violation

EOF A Full A

Bit Name Description

7 Valid B The Valid B bit is true when all the bits in the Receive SERDES Data B register (Reg 0x0B) are valid.

1 = All bits are valid for Receive SERDES Data B.

0 = Not all bits are valid for Receive SERDES Data B.

When data is written into the Receive SERDES Data B register (Reg 0x0B) this bit is set if all of the bits within

the byte that has been written are valid. This bit cannot generate an interrupt.

6 Flow Violation B The Flow Violation B bit is used to signal whether an overflow or underflow condition has occurred for the

Receive SERDES Data B register (Reg 0x0B).

1 = Overflow/underflow interrupt pending for Receive SERDES Data B.

0 = No overflow/underflow interrupt pending for Receive SERDES Data B.

Overflow conditions occur when the radio loads new data into the Receive SERDES Data B register (Reg

0x0B) before the prior data has been read. Underflow conditions occur when trying to read the Receive

SERDES Data B register (Reg 0x0B) when the register is empty. This bit is cleared by reading the Receive

Interrupt Status register (Reg 0x08)

Not Recommended for New Designs

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