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CYWUSB6934

CYWUSB6932

Document Number : 38-16007 Rev. *L Page 6 of 34

DIO Interface

The DIO communications interface is an optional SERDES

bypass data-only transfer interface. In receive mode, DIO and

DIOVAL are valid after the falling edge of IRQ, which clocks the

data as shown in Figure 5. In transmit mode, DIO and DIOVAL

are sampled on the falling edge of the IRQ, which clocks the data

as shown in Figure 6. The application MCU samples the DIO and

DIOVAL on the rising edge of IRQ.

Interrupts

The CYWUSB6932/CYWUSB6934 ICs feature three sets of

interrupts: transmit, receive (CYWUSB6934 only), and a wake

interrupt. These interrupts all share a single pin (IRQ), but can

be independently enabled/disabled. In transmit mode, all receive

interrupts are automatically disabled, and in receive mode all

transmit interrupts are automatically disabled. However, the

contents of the enable registers are preserved when switching

between transmit and receive modes.

Interrupts are enabled and the status read through 6 registers:

Receive Interrupt Enable (Reg 0x07), Receive Interrupt Status

(Reg 0x08), Transmit Interrupt Enable (Reg 0x0D), Transmit

Interrupt Status (Reg 0x0E), Wake Enable (Reg 0x1C), Wake

Status (Reg 0x1D).

If more than 1 interrupt is enabled at any time, it is necessary to

read the relevant interrupt status register to determine which

event caused the IRQ pin to assert. Even when a given interrupt

source is disabled, the status of the condition that would

otherwise cause an interrupt can be determined by reading the

appropriate interrupt status register. It is therefore possible to

use the devices without making use of the IRQ pin at all.

Firmware can poll the interrupt status register(s) to wait for an

event, rather than using the IRQ pin.

The polarity of all interrupts can be set by writing to the Configu-

ration register (Reg 0x05), and it is possible to configure the IRQ

pin to be open drain (if active low) or open source (if active high).

Wake Interrupt

When the PD pin is low, the oscillator is stopped. After PD is

deasserted, the oscillator takes time to start, and until it has done

so, it is not safe to use the SPI interface. The wake interrupt

indicates that the oscillator has started, and that the device is

ready to receive SPI transfers.

The wake interrupt is enabled by setting bit 0 of the Wake Enable

pending is indicated by the state of bit 0 of the Wake Status

(Reg 0x1D) clears the interrupt.

Transmit Interrupts

Four interrupts are provided to flag the occurrence of transmit

events. The interrupts are enabled by writing to the Transmit

Interrupt Enable register (Reg 0x0D), and their status may be

determined by reading the Transmit Interrupt Status register

(Reg 0x0E). If more than 1 interrupt is enabled, it is necessary to

read the Transmit Interrupt Status register (Reg 0x0E) to

determine which event caused the IRQ pin to assert.

The function and operation of these interrupts are described in

detail in

Section .

Receive Interrupts

Eight interrupts are provided to flag the occurrence of receive

events, four each for SERDES A and B. In 64 chips/bit and 32

chips/bit DDR modes, only the SERDES A interrupts are

available, and the SERDES B interrupts will never trigger, even

if enabled. The interrupts are enabled by writing to the Receive

Interrupt Enable register (Reg 0x07), and their status may be

determined by reading the Receive Interrupt Status register (Reg

0x08). If more than one interrupt is enabled, it is necessary to

read the Receive Interrupt Status register (Reg 0x08) to

determine which event caused the IRQ pin to assert.

The function and operation of these interrupts are described in

detail in

Section .

Figure 5. DIO Receive Sequence

Figure 6. DIO Transmit Sequence

DIOVAL

DIO

IRQ

d7d6d5d4d3d2

d...d14d13d12d11d10

d9d8

d1d0

data to mcu

v7v6v5v4v3v2

v...v14v13v12v11v10

v9v8

v1v0

DIOVAL

DIO

IRQ

d7d6d5d4d3d2

d...d14d13d12d11d10

d9d8

d1d0

data from mcu

v7v6v5v4v3v2

v...v14v13v12v11v10

v9v8

v1v0

Not Recommended for New Designs

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