Cypress Semiconductor enCoRe CY7C601xx Betriebsanweisung PDF herunterladen (Seite 29)

CY7C601xx

CY7C602xx

Document 38-16016 Rev. *C Page 29 of 62

Figure 8. Sleep Timing

Wakeup Sequence

Once asleep, the only event that can wake the system up is

an interrupt. The global interrupt enable of the CPU flag

wake the system up. It is optional for the CPU to actually take

the interrupt after the wakeup sequence. The wakeup

sequence is synchronized to the 32 kHz clock for purposes of

sequencing a startup delay, to allow the Flash memory module

enough time to power up before the CPU asserts the first read

access. Another reason for the delay is to allow the oscillator,

Bandgap, and LVD/POR circuits time to settle before actually

being used in the system. As shown in Figure 9, the wakeup

sequence is as follows:

1. The wakeup interrupt occurs and is synchronized by the

negative edge of the 32 kHz clock.

2. At the following positive edge of the 32 kHz clock, the

system wide PD signal is negated. The Flash memory

module, internal oscillator, EFTB, and bandgap circuit are

all powered up to a normal operating state.

3. At the following positive edge of the 32 kHz clock, the

current values for the precision POR and LVD have settled

and are sampled.

4. At the following negative edge of the 32 kHz clock (after

about 15 µs nominal), the BRQ signal is negated by the

sleep logic circuit. On the following CPUCLK, BRA is

negated by the CPU and instruction execution resumes.

Note that in Figure 9 fixed function blocks, such as Flash,

internal oscillator, EFTB, and bandgap, have about 15 µs

start up. The wakeup times (interrupt to CPU operational)

will range from 75 µs to 105 µs.

Firmware write to SCR

SLEEP bit causes an

immediate BRQ

IOW

SLEEP

BRQ

BRA

CPUCLK

CPU captures

BRQ on next

CPUCLK edge

CPU

responds

with a BRA

On the falling edge of

CPUCLK, PD is asserted.

The 24/48 MHz system clock

is halted; the Flash and

bandgap are powered down

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