Cypress Semiconductor enCoRe CY7C601xx Betriebsanweisung Seite 55
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CY7C601xx
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Document 38-16016 Rev. *C Page 55 of 62
Figure 18. Clock Timing
Figure 19. GPIO Timing Diagram
SPI Timing
T
SMCK
SPI Master Clock Rate F
CPUCLK
/6 2 MHz
T
SSCK
SPI Slave Clock Rate 2.2 MHz
T
SCKH
SPI Clock High Time High for CPOL = 0, Low for CPOL = 1 125 ns
T
SCKL
SPI Clock Low Time Low for CPOL = 0, High for CPOL = 1 125 ns
T
MDO
Master Data Output Time
[5]
SCK to data valid –25 50 ns
T
MDO1
Master Data Output Time,
First bit with CPHA = 0
Time before leading SCK edge 100 ns
T
MSU
Master Input Data Setup time 50 ns
T
MHD
Master Input Data Hold time 50 ns
T
SSU
Slave Input Data Setup Time 50 ns
T
SHD
Slave Input Data Hold Time 50 ns
T
SDO
Slave Data Output Time SCK to data valid 100 ns
T
SDO1
Slave Data Output Time,
First bit with CPHA = 0
Time after SS LOW to data valid 100 ns
T
SSS
Slave Select Setup Time Before first SCK edge 150 ns
T
SSH
Slave Select Hold Time After last SCK edge 150 ns
AC Characteristics (continued)
Parameter Description Conditions Min. Typical Max. Unit
Note
5. In Master mode first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.
CLOCK
T
CYC
T
CL
T
CH
10%
T
R_GPIO
T
F_GPIO
GPIO Pin Output
Voltage
90%
- Microcontrolle 1
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