CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C Page 45 of 62
Table 70.Capture Interrupt Enable (TCAPINTE) [0x2B] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Reserved Cap1 Fall
Enable
Cap1 Rise
Enable
Cap0 Fall
Enable
Cap0 Rise
Enable
Read/Write ––––R/W R/W R/W R/W
Default 0 0 0 0 000 0
Bit [7:4]: Reserved
Bit 3: Cap1 Fall Enable
0 = Disable the capture 1 falling edge interrupt
1 = Enable the capture 1 falling edge interrupt
Bit 2: Cap1 Rise Enable
0 = Disable the capture 1 rising edge interrupt
1 = Enable the capture 1 rising edge interrupt
Bit 1: Cap0 Fall Enable
0 = Disable the capture 0 falling edge interrupt
1 = Enable the capture 0 falling edge interrupt
Bit 0: Cap0 Rise Enable
0 = Disable the capture 0 rising edge interrupt
1 = Enable the capture 0 rising edge interrupt
Table 71.Timer Capture 0 Rising (TCAP0R) [0x22] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Capture 0 Rising [7:0]
Read/Write R R R R RRR R
Default 0 0 0 0 000 0
Bit [7:0]: Capture 0 Rising [7:0]
This register holds the value of the Free-running Timer when the last rising edge occurred on the TCAP0 input. When Capture 0
is in 8-bit mode, the bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When
Capture 0 is in 16-bit mode this register holds the lower order 8 bits of the 16-bit timer.
Table 72.Timer Capture 1 Rising (TCAP1R) [0x23] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Capture 1 Rising [7:0]
Read/Write R R R R RRR R
Default 0 0 0 0 000 0
Bit [7:0]: Capture 1 Rising [7:0]
This register holds the value of the Free-running Timer when the last rising edge occurred on the TCAP1 input. The bits that are
stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When Capture 0 is in 16-bit mode this
register holds the high-order 8 bits of the 16-bit timer from the last Capture 0 rising edge. When Capture 0 is in 16-bit mode this
register will be loaded with the high-order 8 bits of the 16-bit timer on TCAP0 rising edge.
Table 73.Timer Capture 0 Falling (TCAP0F) [0x24] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Capture 0 Falling [7:0]
Read/Write R R R R RRR R
Default 0 0 0 0 000 0
Bit [7:0]: Capture 0 Falling [7:0]
This register holds the value of the Free-running Timer when the last falling edge occurred on the TCAP0 input. When Capture
0 is in 8-bit mode, the bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When
Capture 0 is in 16-bit mode this register holds the lower order 8 bits of the 16-bit timer.
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