CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C Page 35 of 62
P0.0/CLKIN Configuration
P0.1/CLKOUT Configuration
Table 49.P0.0/CLKIN Configuration (P00CR) [0x05] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Reserved Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull-up Enable Output Enable
Read/Write – R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 000 0
This pin is shared between the P0.0 GPIO use and the CLKIN pin for the external crystal oscillator. When the external oscillator
is enabled the settings of this register are ignored.
The alternate function of the pin as the CLKIN is only available in the CY7C601xx. When the external oscillator is enabled (the
XOSC Enable bit of the CLKIOCR Register is set—Table 34), the GPIO function of the pin is disabled.
The 50-mA sink drive capability is only available in the CY7C601xx. In the CY7C602xx, only 8-mA sink drive capability is available
on this pin regardless of the setting of the High Sink bit.
If this pin is used as a General Purpose output it will draw current. This pin should be configured as an input to reduce current draw.
Table 50.P0.1/CLKOUT Configuration (P01CR) [0x06] R/W]
Bit # 7 6 5 4 3 2 1 0
Field CLK Output Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull-up Enable Output Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 000 0
This pin is shared between the P0.1 GPIO use and the CLKOUT pin for the external crystal oscillator. When the external oscillator
is enabled the settings of this register are ignored. When CLK output is set, the internally selected clock is sent out onto
P0.1CLKOUT pin.
The alternate function of the pin as the CLKOUT is only available in the CY7C601xx. When the external oscillator is enabled
(the XOSC Enable bit of the CLKIOCR Register is set—Table 34), the GPIO function of the pin is disabled.
The 50-mA sink drive capability is only available in the CY7C601xx. In the CY7C602xx, only 8-mA sink drive capability is available
on this pin regardless of the setting of the High Sink bit.
If this pin is used as a General Purpose output it will draw current. This pin should be configured as an input to reduce current draw
Bit 7: CLK Output
0 = The clock output is disabled
1 = The clock selected by the CLK Select field (Bit [1:0] of the CLKIOCR Register—Table 34) is driven out to the pin
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