Cypress Semiconductor ISR 37000 CPLD Spezifikationen PDF herunterladen

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600

November 9, 2001

Design Considerations for In-System Reprogrammable

™

(ISR

™

) Programming of Cypress CPLDs

Introduction

The In-System Reprogrammable

™

(ISR

™

) feature of Cypress

Complex Programmable Logic Devices (CPLDs) enables re-

configurability of devices while soldered onto a system board.

A standard IEEE 1149.1 (JTAG) interface is available to facil-

itate device configuration as well as boundary scan opera-

tions for straightforward prototyping, production program and

test, field update, and general-purpose applications (note the

LASH

370i™ family does not support boundary scan). The

purpose of this application note is to detail applicable board

design considerations and offer specific design guidance in

order to simplify development of systems employing ISR ca-

pabilities.

The simplest method for integrating ISR functionality into a

system is to interface directly to a Cypress ISR PC cable.

Seamless PC control is provided by simply tying the ISR sig-

nals to an ISR header. While sections of this application note

discuss specifics of the Cypress ISR PC cables, the design

considerations pertaining to CPLD family or board level is-

sues are implementation-generic and are directly applicable

with any method of In-System Reprogrammable configura-

tion, be it control via ISR PC cable, automated test equipment

(ATE), or embedded microprocessor. The guidelines dis-

cussed herein are general and apply to any ISR interface

methodology. For example, proper ISR signal layout and ter-

mination practices should be followed to ensure good signal

integrity and reprogramming reliability. This involves aware-

ness of device drive capabilities and transmission line effects

pertaining to critical ISR signal distribution.

The In-System Reprogrammable feature is available in Cy-

press’s Delta39K

™

, Quantum38K

™

, Ultra37000(V)

™

, and

LASH

370i CPLD families, as well as Cypress’s Programma-

ble Serial Interface

™

(PSI

™

) programmable PHY family. Differ-

ences between product families yield certain device-specific

design considerations. For example, Delta39K, Quantum38K

and PSI devices all offer 3.3V, 2.5V, and 1.8V I/O standard

configurations for the ISR interface, whereas Ultra37000 of-

fers 5V and 3.3V capability. Additionally, certain compact

package options with the Ultra37000(V) and F

LASH

370i

CPLDs allow dual-function ISR pins to switch between pro-

gramming and regular I/O modes. These device-specific dif-

ferences and their implications on ISR chain configuration are

discussed herein.

This application note discusses transmission line effects that

can arise from the ISR chain, which can cause signal integrity

problems, and provides suggestions for trace layout to mini-

mize these effects. Transmission line effects are inherent in

the ISR programming set-up due to impedance mismatching

between the ISR programming source (such as an ISR ca-

ble), traces and trace layout on the PCB, and ISR devices

themselves. Properly terminated discrete buffers on the PCB,

while not required in most cases, produce the highest quality

waveforms and provide the best solution to controlling trans-

mission line effects.

This note also discusses all issues related to programming

and reprogramming the devices in-system (i.e., while they are

soldered onto a printed circuit board). These issues include:

an explanation of the available ISR programming cables and

ISR connections, using the ISR programming pins for both

functional logic and for programming, connecting ISR devices

in a chain for programming as well as proper functional oper-

ation.

For the purpose of this note, “ISR device” refers to any ISR-

capable device family. Also, “Ultra37000(V)” refers to both 5V

Ultra37000 and 3.3V Ultra37000V. This design consider-

ations note complements other Cypress ISR application

notes, which offer introductory or device-specific information.

ISR Programming Pins

The programming pins for the Delta39K, Quantum38K, and

PSI devices are standard JTAG signals: TDI, TDO, TMS, and

TCK. Ultra37000(V) CPLDs include these pins, plus an addi-

tional control pin called JTAGen in some device packages. For

the F

LASH

370i family, the same pins are named SDI, SDO,

SMODE, SCLK, and ISRen respectively. The reason for using

the standard JTAG naming convention for most ISR devices

is that these families support Boundary Scan testing and are

compliant with the IEEE 1149.1 (JTAG) standard. The pro-

gramming interface for the F

LASH

370i devices also complies

with most of the standard; however, these devices do not sup-

port boundary scan so the names were changed from the

standard JTAG naming convention to prevent misleading the

user. For the purposes of this note the JTAG pin nomenclature

is used.

All ISR devices can be cascaded into a single chain for pro-

gramming purposes so that one programming source (such

as an ISR PC cable) can program all of the ISR devices on a

board. The pins on an ISR device used for programming are:

JTAGen, TDI, TDO, TMS, and TCK. Their names and func-

tions are defined below.

TDI (SDI) – Data Input

During programming, this pin provides the serial data input to

the device.

TDO (SDO) – Data Output

During programming, this pin provides the serial data output

from the device.

TCK (SCLK) – Clock

During programming, this pin is the clock input. TDI and TMS

are sampled on the rising edge of TCK, while TDO changes

following the falling edge of TCK.

1 2 3 4 5 6 ... 19 20

Inhaltsverzeichnis

Seite 1 - ISR Programming Pins

Cypress Semiconductor Corporation• 3901 North First Street • San Jose • CA 95134 • 408-943-2600November 9, 2001Design Considerations for In-System Re

Seite 2 - TO 10–PIN CONNECTOR ON BOARD

Design Considerations for ISR Programming of Cypress CPLDs10The value of this pull-down resistor for TCK is not crucial sincethe external JTAG pin dri

Seite 3

Design Considerations for ISR Programming of Cypress CPLDs11Appendix A. Dual-Function Device Considerations for Ultra37000 and FLASH370i CPLDsOnly the

Seite 4

Design Considerations for ISR Programming of Cypress CPLDs12pins as I/Os in normal operation because their physical posi-tion makes your board layout

Seite 5 - Simple ISR Device Cascading

Design Considerations for ISR Programming of Cypress CPLDs13ers or pass-transistors from a 74FCT244T or a Texas Instru-ments SN74CBT3384A, for example

Seite 6 - Board Layout Considerations

Design Considerations for ISR Programming of Cypress CPLDs14ISR*. By implementing this inversion, the inverter in Figure14(e) can be removed, and pin

Seite 7 - TCK Buffer

Design Considerations for ISR Programming of Cypress CPLDs15To understand why this is necessary, consider just combiningthe logic from Figure 14(b) an

Seite 8

Design Considerations for ISR Programming of Cypress CPLDs16Dual-Function SummaryTo summarize this section, there are many ways to accom-plish program

Seite 9

Design Considerations for ISR Programming of Cypress CPLDs17Appendix B. Simple Cascading Considerations for Ultra37000 and FLASH370i CPLDsYou can casc

Seite 10 - References

Design Considerations for ISR Programming of Cypress CPLDs18tion devices. For the FLASH370i it is permissible to actually letthe JTAGen pin float to r

Seite 11 - 370i CPLDs

Design Considerations for ISR Programming of Cypress CPLDs1910-kΩ resistor on the ISR* signal is required to keep the muxinput HIGH when the ISR cable

Seite 12

Design Considerations for ISR Programming of Cypress CPLDs2TMS (SMODE) – Mode ControlDuring programming, this is the mode control input that di-rects

Seite 13

Design Considerations for ISR Programming of Cypress CPLDs© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to ch

Seite 14

Design Considerations for ISR Programming of Cypress CPLDs3The C3ISR cable offers the most flexible choice of program-ming voltage and device support.

Seite 15

Design Considerations for ISR Programming of Cypress CPLDs4 Dimension of the ISR CablesThe C3ISR programming cable consists of a six-foot IEEE-1284 sh

Seite 16

Design Considerations for ISR Programming of Cypress CPLDs5To program a single ISR device using any ISR programmingcable described here, route the TDI

Seite 17

Design Considerations for ISR Programming of Cypress CPLDs6Board Layout ConsiderationsTransmission line effects are a critical design consideration to

Seite 18

Design Considerations for ISR Programming of Cypress CPLDs7divider effect between the source impedance of the buffer andthe characteristic impedance o

Seite 19

Design Considerations for ISR Programming of Cypress CPLDs8to the manufacturing difficulty of fabricating traces with widelyvarying impedance on the s

Seite 20 - Appendix C. Additional F

Design Considerations for ISR Programming of Cypress CPLDs9Device-Specific ISR Design ConsiderationsThe In-System Reprogammability feature is availabl

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