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Chapter 9. Slave FIFOs Page 9-1

Chapter 9 Slave FIFOs

9.1 Introduction

Although some FX2-based devices may use the FX2’s CPU to process USB data directly (see

Chapter 8 "Access to Endpoint Buffers"

), most will use the FX2 simply as a conduit between the

USB and external data-processing logic (e.g., an ASIC or DSP, or the IDE controller on a hard disk

drive).

In devices with external data-processing logic, USB data flows between the host and that external

logic —

usually without any participation by the FX2’s CPU

— through the FX2’s internal

endpoint

FIFOs

. To the external logic, these endpoint FIFOs look like most others; they provide the usual

timing signals, handshake lines (full, empty, programmable-level), read and write strobes, output

enable, etc.

These FIFO signals must, of course, be controlled by a FIFO “master”. The FX2’s General Pro-

grammable Interface (GPIF) can act as an internal master when the FX2 is connected to external

logic which doesn’t include a standard FIFO interface, or the FIFOs can be controlled by an exter-

nal master. While its FIFOs are controlled by an external master, the FX2 is said to be in “Slave

FIFO” mode.

Chapter 10, "General Programmable Interface (GPIF)," discusses the internal-master GPIF. This

chapter provides details on the interface — both hardware and software — between the FX2’s

slave FIFOs and an external master.

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