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EZ-USB FX2 Technical Reference Manual

Page 1-12 EZ-USB FX2 Technical Reference Manual v2.1

The FIFOs can be controlled by an external master, which either supplies a clock and clock-

enable signals to operates synchronously, or strobe signals to operate asynchronously.

Alternately, the FIFOs can be controlled by an internal FX2 timing generator called the General

Programmable Interface (GPIF). The GPIF serves as an internal master, interfacing directly to the

FIFOs and generating user-programmed control signals for the interface to external logic. Addi-

tionally, the GPIF can be made to wait for external events by sampling external signals on its RDY

pins. The GPIF runs much faster than the FIFO data rate to give good programmable resolution

for the timing signals. It can be clocked from either the internal FX2 clock or an externally supplied

clock.

The FX2’s CPU is rich in features. Up to five I/O ports are available, as well as two USARTs, three

counter/timers, and an extensive interrupt system. It runs at a clock rate of up to 48 MHz and uses

four clocks per instruction cycle instead of the twelve required by a standard 8051.

The FX2 chip family uses an enhanced SIE/USB interface which simplifies FX2 code by imple-

menting much of the USB protocol. In fact, the FX2 can function as a full USB device even without

firmware.

Like all EZ-USB family chips, FX2 operates at 3.3V. This simplifies the design of bus-powered

USB devices, since the 5V power available at the USB connector (which the USB Specification

allows to be as low as 4.4V) can drive a 3.3V regulator to deliver clean, isolated power to the FX2

chip.

Figure 1-8. FX2 128-pin Package Simplified Block Diagram

FX2 is available in a 128-pin package which brings out the 8051 address bus, data bus, and con-

trol signals to allow connection of external memory and/or memory-mapped I/O. Figure 1-8 is a

block diagram for this package; Chapter 5, "Memory", gives full details of the external-memory

interface.

Serial

Interface

Engine

(SIE)

USB

Transceiver

D+

D-

USB

Connector

OUT

data

USB

Interface

Slave

FIFOs

Program &

Data

RAM

EZ-USB FX2

GPIF

CTL RDY

Address Bus

Data Bus

Off-Chip

Memory

I/O Ports

CPU

(Enhanced

8051)

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