Cypress Semiconductor FX2LP Technical Information PDF herunterladen (Seite 188)

EZ-USB FX2 Technical Reference Manual

Page 9-32 EZ-USB FX2 Technical Reference Manual v2.1

9.3.10 Auto-Mode Example: Synchronous FIFO IN Data Transfers

Figure 9-44. Code Example, Synchronous Slave FIFO IN Data Transfer

TD_Init():

REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1

SYNCDELAY;

FIFORESET = 0x80; // reset all FIFOs

SYNCDELAY;

FIFORESET = 0x02;

SYNCDELAY;

FIFORESET = 0x04;

SYNCDELAY;

FIFORESET = 0x06;

SYNCDELAY;

FIFORESET = 0x08;

SYNCDELAY;

FIFORESET = 0x00;

SYNCDELAY; // this defines the external interface to be the following:

IFCONFIG = 0x43; // use IFCLK pin driven by external logic (5MHz to 48MHz)

// use slave FIFO interface pins driven sync by external master

EP8FIFOCFG = 0x0C; // this lets the FX2 auto commit IN packets, gives the

// ability to send zero length packets,

// and sets the slave FIFO data interface to 8-bits

EP8CFG = 0xE0; // sets EP8 valid for IN's

// and defines the endpoint for 512 byte packets, 2x buffered

PINFLAGSAB = 0x00; // defines FLAGA as prog-level flag, pointed to by FIFOADR[1:0]

SYNCDELAY; // FLAGB as full flag, as pointed to by FIFOADR[1:0]

PINFLAGSCD = 0x00; // FLAGC as empty flag, as pointed to by FIFOADR[1:0]

// won't generally need FLAGD

PORTACFG = 0x00; // used PA7/FLAGD as a port pin, not as a FIFO flag

FIFOPINPOLAR = 0x00; // set all slave FIFO interface pins as active low

SYNCDELAY;

EP8AUTOINLENH = 0x02; // you can define these as you wish,

SYNCDELAY; // to have the FX2 automatically limit IN's

EP8AUTOINLENL = 0x00;

SYNCDELAY;

EP8FIFOPFH = 0x82; // you can define the programmable flag (FLAGA)

SYNCDELAY; // to be active at the level you wish

EP8FIFOPFL = 0x00;

SYNCDELAY; // out endpoints do not POR (power-on reset) armed

EP2BCL = 0x80; // since the defaults are double buffered we must

SYNCDELAY; // write dummy byte counts twice

EP2BCL = 0x80; // arm EP2OUT & EP4OUT by writing to the byte count w/skip.

SYNCDELAY;

EP4BCL = 0x80;

SYNCDELAY;

EP4BCL = 0x80;

TD_Poll():

// nothing! The FX2 is doing all the work of transferring packets

// from the external master sync interface to the endpoint buffer...

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