Cypress Semiconductor FX2LP Technical Information PDF herunterladen (Seite 43)

Chapter 1. Introducing EZ-USB FX2 Page 1-17

1.16.2 100-Pin Package

The 100-pin package adds functionality to the 56-pin package:

• Two additional 8-bit I/O ports: PORTC and PORTE

• Seven additional GPIF Control (CTL) and Ready (RDY) signals

• Nine non-multiplexed peripheral signals (two USARTs, three timer inputs, INT4, and INT5

)

• Eight additional control signals multiplexed onto PORTE

• Nine GPIF address lines, multiplexed onto PORTC (eight) and PORTE (one)

•RD

and WR signals which may be used as read and write strobes for PORTC

1.16.3 128-Pin Package

The 128-pin package adds the 8051 address and data buses and control signals. The RD, PSEN,

and WR

strobes are standard 8051 control strobes, serving as read/write strobes for external

memory attached to the 8051 address and data buses. The FX2 encodes the CS

and OE signals

to automatically exclude external access to memory spaces which exist on-chip, and optionally to

combine off-chip data- and code-memory read accesses. The 128-pin package adds the following:

• 16-bit 8051 address bus

• 8-bit 8051 data bus

• Address/data bus control signals

1.16.4 Signals Available in the Three Packages

Three interface modes are available: Ports, GPIF Master, and Slave FIFO.

Figure 1-11 shows a logical diagram of the signals available in the three packages. The signals on

the left edge of the diagram are common to all interface modes, while the signals on the right are

specific to each mode. The interface mode is software-selectable via an internal mode register.

In “Ports” mode, all the I/O pins are general-purpose I/O ports.

“GPIF master” mode uses the PORTB and PORTD pins as a 16-bit data interface to the four FX2

endpoint FIFOs EP2, EP4, EP6 and EP8. In this “master” mode, the FX2 FIFOs are controlled by

the internal GPIF, a programmable waveform generator that responds to FIFO status flags, drives

timing signals using its CTL outputs, and waits for external conditions to be true on its RDY inputs.

Note that only a subset of the GPIF signals (CTL0-2, RDY0-1) is available in the 56-pin package,

while the full set (CTL0-5, RDY0-5) is available in the 100- and 128-pin packages.

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Cypress Semiconductor FX2LP Technical Information Seite 43