
Chapter 13. Input/Output Page 13-13
Figure 13-7. Addressing an I²C Peripheral
Each peripheral (slave) device on the I²C bus has a unique address. The first byte of an I²C trans-
action contains the address of the desired peripheral. Figure 13-7 shows the format for this first
byte, which is sometimes called a
control
byte.
The FX2 sends the bit sequence shown in Figure 13-7 to select the peripheral at a particular
address, to establish the transfer direction (using R/W
), and to determine if the peripheral is
present by testing for ACK
.
The four most significant bits (SA3:0) are the peripheral chip’s slave address. I²C devices are pre-
assigned slave addresses by device type. Slave address 1010, for example, is assigned to
EEPROMs. The next three bits (DA2:0) usually reflect the states of the peripheral’s device address
pins. Devices with three address pins can be strapped to allow eight distinct addresses for the
same device type, which allows, for example, up to eight identical serial EEPROMs to be individu-
ally addressed.
The eighth bit (R/W
) sets the direction for the ensuing data transfer (1 = master read, 0 = master
write). Most address transfers are followed by one or more data transfers, with the STOP condition
generated after the last data byte is transferred.
In Figure 13-7, a READ transfer follows the address byte (at clock 8, the master sets the R/W
bit
high, indicating READ). At clock 9, the peripheral device responds to its address by asserting ACK
.
At clock 10, the master floats SDA and issues SCL pulses to clock in SDA data supplied by the
slave.
13.4.2 Registers
The three registers shown in Figur e13-8 are used to conduct transfers over the I²C-compatible
bus.
Data is transferred to and from the bus through the I2DAT register. The I2CS register controls the
transfers and reports various status conditions. I2CTL configures the bus.
123456
7
8 9
SA3 ACKSA2 SA1 SA0 DA2 DA1 DA0
start
SDA
D7 D6
10 11
R/W
SCL
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