Cypress Semiconductor FX2LP Technical Information PDF herunterladen (Seite 166)

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EZ-USB FX2 Technical Reference Manual

Page 9-10 EZ-USB FX2 Technical Reference Manual v2.1

9.2.6 Slave FIFO Chip Select (SLCS)

The “Slave FIFO Chip Select” pin (SLCS) is an alternate function of pin PA7; it’s enabled via the

PORTACFG.6 bit (see Section 13.3.1, "Port A Alternate Functions").

The SLCS

pin allows external logic to effectively remove the FX2 from the FIFO Data bus, in order

to, for example, share that bus among multiple slave devices.

While the SLCS

pin is pulled high by external logic, the FX2 floats its FD[x:0] pins and ignores the

SLOE, SLRD, SLWR, and PKTEND pins.

9.2.7 Implementing Synchronous Slave FIFO Writes

Figure 9-10. Interface Pins Example: Synchronous FIFO Writes

Typically, the sequence of events for the external master is:

IDLE: When write event occurs, transition to State 1.

STATE 1: Point to IN FIFO, assert FIFOADR[1:0], transition to State 2.

STATE 2: If FIFO-Full flag is false (FIFO not full), transition to State 3 else remain in State 2.

STATE 3: Drive data on the bus, assert SLWR for one IFCLK, transition to State 4.

STATE 4: If more data to write, transition to State 2 else transition to IDLE.

IFCLK

FLAGB

FLAGC

SLWR

PKTEND

FIFOADR[1:0]

FD[15:0]

FX2

Slave

Mode

EXT.

Master

FULL

EMPTY

5-48MHz

1 2 ... 161 162 163 164 165 166 167 168 169 170 171 ... 459 460

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