Cypress Semiconductor FX2LP Technical Information PDF herunterladen (Seite 339)

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Chapter 15. Registers Page 15-19

NOTE: FLAGD defaults to EP2PF (fixed flag).

For the default (0000) selection, the four FIFO flags are indexed as shown in the first table entry.

The input pins FIFOADR1 and FIFOADR0 select to which of the four FIFOs the flags correspond.

These pins are decoded as follows:

Table 15-10. FIFOADR1 FIFOADR0 Pin Correspondence

For example, if FLAGA[3:0]=0000 and the FIFO address pins are driven to [01], then FLAGA is the

EP4-Programmable Flag, FLAGB is the EP4-Full Flag, and FLAGC is the EP4-Empty Flag, and

FLAGD defaults as PA7. Set PORTACFG.7 = 1 to use FLAGD which by default is EP2PF(fixed

flag).

The other (non-zero) values of FLAGx[3:0] allow the designer to independently configure the four

flag outputs FLAGA-FLAGD to correspond to any flag—Programmable, Full, or Empty—from any

of the four endpoint FIFOS. This allows each flag to be assigned to any of the four FIFOS, includ-

ing those not currently selected by the FIFOADDR pins. For example, external logic could be filling

the EP2IN FIFO with data while also checking the full flag for the EP4OUT FIFO.

Table 15-9. FIFO Flag Pin Functions

FLAGx3 FLAGx2 FLAGx1 FLAGx0 Pin Function

0 0 0 0

FLAGA=PF, FLAGB=FF, FLAGC=EF,

FLAGD=EP2PF (Actual FIFO is selected

by FIFOADR[0,1] pins)

0 0 0 1

0 0 1 0 Reserved

0 0 1 1

0 1 0 0 EP2 PF

0 1 0 1 EP4 PF

0 1 1 0 EP6 PF

0 1 1 1 EP8 PF

1 0 0 0 EP2 EF

1 0 0 1 EP4 EF

1 0 1 0 EP6 EF

1 0 1 1 EP8 EF

1 1 0 0 EP2 FF

1 1 0 1 EP4 FF

1 1 1 0 EP6 FF

1 1 1 1 EP8 FF

FIFOADR1 pin FIFOADR0 pin Selected FIFO

0 0 EP2

0 1 EP4

1 0 EP6

1 1 EP8

1 2 ... 334 335 336 337 338 339 340 341 342 343 344 ... 459 460

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