Cypress Semiconductor FX2LP Technical Information PDF herunterladen (Seite 363)

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Chapter 15. Registers Page 15-43

15.7 Interrupts

15.7.1 Endpoint 2, 4, 6, 8 Slave FIFO Flag Interrupt Enable/Request

Figure 15-37. Endpoint 2, 4, 6, 8 Slave FIFO Flag Interrupt Enable

The Interrupt Registers control all the FX2 Interrupt Enables (IE) and Interrupt requests (IRQ).

Interrupt enables and request bits for endpoint FIFO: Programmable Flag (PF), Empty Flag (EF),

and Full Flag (FF).

To enable any of these interrupts, INTSETUP.1 (INT4SRC) and INTSETUP.0 must be ‘1’.

Bit 3 EDGEPF Firing Edge Programmable Flag

When EDGEPF=0, the interrupt fires on the rising edge of the programmable flag.

When EDGEPF=1, the interrupt fires on the falling edge of the programmable flag.

Note: In order for the CPU to vector to the appropriate interrupt service routine, PF must

be set to a “1“ and INTSETUP.0=1 (AV4EN) and INTSETUP.1=1 (INT4SRC). Refer to Sec-

tion 15.7.12

Bit 2 PF Programmable Flag

When this bit is '1', the programmable flag interrupt is enabled on INT4. When this bit is '0' the

programmable flag interrupt is disabled.

EP2FIFOIE

see Section 15.14

EP2 Slave FIFO Flag Interrupt Enable (INT4) E650

EP4FIFOIE

see Section 15.14

EP4 Slave FIFO Flag Interrupt Enable (INT4) E652

EP6FIFOIE

see Section 15.14

EP6 Slave FIFO Flag Interrupt Enable (INT4) E654

EP8FIFOIE

see Section 15.14

EP8 Slave FIFO Flag Interrupt Enable (INT4) E656

b7 b6 b5 b4 b3 b2 b1 b0

0 0 0 0 EDGEPF PF EF FF

R/W R/W R/W R/W R/W R/W R/W R/W

0 0 0 0 0 0 0 0

1 2 ... 358 359 360 361 362 363 364 365 366 367 368 ... 459 460

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