Cypress Semiconductor FX2LP Technical Information PDF herunterladen (Seite 336)

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EZ-USB FX2 Technical Reference Manual

Page 15-16 EZ-USB FX2 Technical Reference Manual v2.1

Bit 3 ASYNC FIFO/GPIF Asynchronous Mode

When ASYNC=0, the FIFO/GPIF operate synchronously: a clock is supplied either internally

or externally on the IFCLK pin; the FIFO control signals function as read and write enable sig-

nals for the clock signal.

When ASYNC=1, the FIFO/GPIF operate asynchronously: no clock signal input to IFCLK is

required; the FIFO control signals function directly as read and write strobes.

Bit 2 GSTATE Drive GSTATE [2:0] on PORTE [2:0]

When GSTATE=1, three bits in Port E take on the signals shown in Table 15-6. The GSTATE

bits, which indicate GPIF states, are used for diagnostic purposes.

Bit 1-0 IFCFG1:0 Select Interface Mode (Ports, GPIF, or Slave FIFO)

These bits control the following FX2 interface signals, as shown in Tabl e15-8.

Table 15-6. Port E Alternate Functions When GSTATE=1

IO Pin Alternate Function

PE0 GSTATE[0]

PE1 GSTATE[1]

PE2 GSTATE[2]

Table 15-7. Ports, GPIF, Slave FIFO Select

IFCFG1 IFCFG0 Configuration

0 0 Ports

0 1 Reserved

1 0 GPIF Interface (internal

master)

1 1 Slave FIFO Interface

(external master)

1 2 ... 331 332 333 334 335 336 337 338 339 340 341 ... 459 460

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