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5.1.2 VHDL Simulation

Simulation is an important part of the logic development process. All designs that are targeted at

using the large logic devices supported by the Framework Logic require simulation for successful

implementation. If you do not simulate your design, it is unlikely that you will successfully complete

it during your lifetime.

For simulation, we are currently supporting ModelSim 6.1 PE. The Xilinx MXE version cannot be

used since it cannot be used simulate designs as large as the FrameWork Logic designs.

The Framework Logic includes a test bench and models required for most simulations. In many

cases the models are simple representations of the device that give a data pattern that is easy to

follow through the simulations. More complex waveforms can always be substituted later for

proving out the signal processing or data analysis portions of the design. In each design, the list

of files shows the applicable test bench name and available models.

The testbench contains a set of simulation steps that exercise various functions on the framework

logic for basic interface testing. Behavioral procedures have been written to simulate the DSP

timing for sync and asynchronous memory accesses that are useful in simulating data movement.

Also, the steps to setup the logic for data streaming support are shown so that interrupt servicing

(DMA or CPU accesses), trigger and event log use are illustrated.

As delivered, the FrameWork Logic example provides a basic example in the use of the hardware

interface components, data flow through the design, and some simple triggering control. It is

anticipated that you can use this example test bench as a starting point for your application logic

simulation. Your logic can be added to the simulation in many cases without modifying the test

bench since the application logic does not change the external pins on the design.

Before simulation can begin, the pertinent libraries must be compiled for the chip you are

targeting. If you are starting from Xilinx ISE, this is done by selecting the device in the Sources

window, then double-clicking the “Compile HDL Simulation Libraries” process in the Processes

window. This will compile the unisim, simprim and xilixcorelib files necessary for simulation. You

may have to configure this process so that it points at your current ModelSim installation; this is

done by right-clicking and setting the parameters. If you are working with ModelSim standalone,

be sure to compile the libraries unisim, simprim and xilinxcorelib and add them to the libraries in

ModelSim (vlib) before attempting to simulate.

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Cypress Semiconductor Perform CY7C1372D Betriebsanweisung Seite 12