Cypress Semiconductor Perform CY7C1372D Betriebsanweisung PDF herunterladen (Seite 86)

Port Direction Function

Addr[19:0] Out SBSRAM address bits

lbo_n Out SBSRAM burst mode; 0= linear (only mode supported)

Sclk Out 2x clock to SRAM

Cke_n Out SBSRAM clock enable, active low

ld_n Out SBSRAM synchronous address advance/load(low)

bwa_n Out SBSRAM Byte Write A, active low. A low enables a write

to bits 7..0.

bwb_n Out SBSRAM Byte Write B active low. A low enables a write

to bits 15..8.

bwc_n Out SBSRAM Byte Write C, active low. A low enables a

write to bits 23..16.

bwd_n Out SBSRAM Byte Write D, active low. A low enables a

write to bits 31..24.

rw_n Out SBSRAM read/write(low) control

oe_n Out SBSRAM data output enable, active low.

ce_n Out SBSRAM chip enable, active low.

Ce2 Out SBSRAM chip enable.

ce2_n Out SBSRAM chip enable, active low.

zz Out SBSRAM low power mode control.

ui_addr[19:0] In User input address.

ui_write_data[31:0] In User write data inputs.

ui_rw_n In User read/write(low).

ui_rw_n_ctlr In User read/write (low) control. Usually wired to the same

signal as ui_rw_n.

Clk In System clock input

ui_read_data[31:0] out Data read from SBSRAM

write_data_p_sig[31:0] out write data to I/O buffer on top level.

rw_tff_p_sig[31:0] out I/O buffer enable for top level IO buffers.

read_data_sig[31:0] In read data from I/O buffer on top level.

Table 17: ii_quxiote_sbsram Component Ports

The four SRAM devices on Quixote are Cypress CY7C1372 (or equivalent). The

device simulation model is cy7c1372.vhd.

MATLAB Simulink Components:

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Cypress Semiconductor Perform CY7C1372D Betriebsanweisung Seite 86