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7.1.1.3 ii_quixote_dsp_emif_a

Supported Platforms: Quixote

Description:

This component is the DSP External Memory InterFace (EMIF) A bus interface. It provides an

interface between the FPGA and the DSP for data, status and control registers.

This component interfaces with the Texas Instruments TMS320C6416 DSP EMIF A, a 64-bit bus

operating at 100 MHz on Quixote. EMIF A has 4 memory spaces (CE spaces) that are configured

in the DSP initialization for memory type and timing behavior. Two of the memory spaces are

available for DSP interfaces to the logic. These two memory spaces have different setups and

use as shown in the following table.

CE Type Rate Use

0 Asynchronous 6 EMIF clocks per transaction

=> 100 Mhz/6 = 16.67 Mhz

access rate

Control and Status

Registers; not high

performance

1 Synchronous 1 EMIF clock per transaction =>

100MHz access rate during

burst reads and writes. Reads

are 3 clocks latent. Setup cycles

each burst

FIFOs; high performance

interfaces

Table 14: DSP EMIF A use with ii_quixote_emif_a Component

The ii_quxiote_dsp_emif_a component decodes EMIF A CE 0 into 128 read and write strobes that

are used for status and control interfacing to the DSP. These are usually used for registers the

DSP will control or read back. The decodes are not the highest performance interface to the DSP

and should be primarily used for lower performance interfaces such as setup and configuration.

Additionally, an array of registers is provided that the DSP can write to, and an array of status

input registers for the DSP to read. This provides a convenient hook-up of the application logic to

the DSP. See the memory map details for existing register usage.

For high speed data paths between the DSP and application logic, the ii_quixote_dsp_emif_a

component provides input and output FIFOs. The example logic shows the FIFOs being using for

A/D and DAC interface FIFOs. More FIFOs can be added if necessary by changing the generic

num_fifos. The application logic interface to the DSP FIFO provides read/write control and FIFO

levels for implementing data flow control within the application logic. Each FIFO also has a reset

input. Each FIFO consumes 2 block rams in memory.

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Cypress Semiconductor Perform CY7C1372D Betriebsanweisung Seite 79