Cypress Semiconductor Perform CY7C1372D Betriebsanweisung PDF herunterladen (Seite 40)

Another built-in test method is to use data checkers in the logic sprinkled through the data chain

help to spot the source of problems. If you have a missing timing constraint or a clock domain

issue, these can be hard to catch since they may be rare. A data checker gives you a way to look

for bad data and then trigger ChipScope or the logic analyzer. In many cases, rare errors are

impossible to catch without this sort of data checker. This technique has saved time because the

trigger at the bad data point allows you to inspect all the suspect signals and find the culprit.

5.5.2 Xilinx ChipScope

Xilinx offers an excellent tool for debugging FPGA designs call ChipScope. This tool works over

the FPGA JTAG port using any of the standard Xilinx JTAG cables. Software on the PC connects

to a ChipScope logic core that you embed in your logic. This is an optional tool from Xilinx and is

not included in the standard ISE software. For its cost of under $1500, we have found it well worth

the money.

The ChipScope core allows you to monitor internal FPGA signals using triggers and a sample

clock. The number of signals you can monitor and use for triggers is set up when you generate

the ChipScope core. The core size is determined by the number of signals monitored and the

number of samples stored. If the core gets too big, it will affect your design and tends to muddle

the debug process. Sometimes it is better to have a small core that has a small footprint and

does not interfere with the other logic for this reason.

The clock is used as the sample clock for the logic so it should be synchronous to the inputs

signals or sufficiently fast to sample them accurately. The size of the core

You will interact with the ChipScope software over a JTAG cable to the target device. This link is

limited to about 4-20 Mb/s, so it is not really real-time, but rather just a means to get the data from

the FPGA to the ChipScope software. The signals are captured in the FPGA block RAMs so the

record length is somewhat short being limited in most cases to 256 to 1K points.

Because of these limitations in JTAG speed and capture size, it is important to devise triggering

methods that allow you to catch the error condition. It is common to devise a piece of error

detection logic that serves as a trigger to ChipScope to best use the capture RAM. It is possible

Innovative Integration FrameWork Logic User Guide 40

Illustration 36: Debugging with ChipScope

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Cypress Semiconductor Perform CY7C1372D Betriebsanweisung Seite 40