Cypress Semiconductor Perform CY7C1372D Betriebsanweisung Seite 56

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The Quixote EMIF A memory decodings are arranged so that ACE0 is asynchronous and ACE1 is
synchronous burst memory. Generally speaking, the async peripherals are not used as high
speed devices since this is inherently a slow access protocol - the sync burst memory interface is
at least 4x faster. The following diagrams show the DSP access timing for burst reads and writes.
For slow speed devices such as configuration and control registers, asynchronous access are
used in the Framework Logic. Asynchronous accesses provide the most flexibility in timing control
and are the easiest to use in most designs, albeit the slowest. The EMIF control registers in the
DSP allow the programmer to define SETUP, STROBE and HOLD lengths for the cycle that give
a programmability to the access timing. For more control, the ARDY signal allows the logic
designer to insert additional wait states to the STROBE timing as needed.
For the high speed data paths for A/D and DAC data in the Framework logic, burst accesses from
the DSP provide the highest data rates. The EMIF configuration registers are set for SBSRAM
memory interface timings, and in the logic the FIFOs respond to these signals to deliver data in
continuous bursts. In the burst mode, one data point (64-bits wide) is provided for each clock. As
can be seen from the read and write burst timing diagrams, data is at least two cycles latent from
the control signals for reads, and may be zero for writes. On the ‘6416, a programmable latency
allows the data to be up to 3 cycles latent for either reads or writes. The Framework Logic uses a
latency of 3 for reads and 0 for writes.
Data bursts can be of any length and the Framework logic accommodates any burst length
Innovative Integration FrameWork Logic User Guide 56
Illustration 48: TI DSP Asynchronous Memory Timing (Courtesy of Texas Instruments)
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