Cypress Semiconductor Perform CY7C1372D Betriebsanweisung PDF herunterladen (Seite 89)

Port Direction Function

Reset In System reset.

ref_clk In Reference clock. On Quxiote this is a 10 Mhz clock.

bm_reset In Bus master reset bit. Resets internal registers and

logic.

dsp_beclk In DSP EMIF B clock. Nominally 100 Mhz.

dsp_b_din[15:0] In DSP EMIF B data input.

dsp_b_addr_h[20:16] In DSP EMIF B address bits 20..16.

dsp_b_addr_l[6:1] In DSP EMIF B address bits 6..1.

dsp_b_ce_n[3:0] In DSP EMIF B memory space decodes, active low.

dsp_b_are_n In DSP EMIF B read enable, active low.

dsp_b_awe_n In DSP EMIF B write enable, active low.

dsp_b_aoe_n In DSP EMIF B output enable, active low.

dsp_b_rdout[15:0] Out Data from the logic out to DSP EMIF B data bus.

dsp_b_dout_en Out Data enables from the logic out to DSP EMIF B data

bus top level buffers.

pci_reg_dout[15:0] Out Registered EMIF B data bus to PCI controller.

pci_reg_din[15:0] In Registered data from PCI controller to the EMIF B data

bus.

pci_reg_a_high[20:16] Out Registered DSP EMIF B address bits 20..16.

pci_reg_a_low[6:1] Out Registered DSP EMIF B address bits 6..1.

pci_reg_bce1_n Out Registered DSP EMIF B memory space decodes, active

low.

pci_reg_bare_n Out Registered DSP EMIF B read enable, active low.

pci_reg_bawe_n Out Registered DSP EMIF B write enable, active low.

pci_reg_baoe_n Out Registered DSP EMIF B output enable, active low.

pci_wrfifo_blen_wr In PCI write FIFO burst length write. This is the write

enable to the interrupt burst counter control.

pci_wrfifo_blen[6:0] In The PCI write FIFO burst length count. This is used to

control the interrupt behavior so that once an interrupt is

signaled, it can only be reasserted after this number of

points are written.

fifo_wr_d[15:0] Out Data bus to the PCI write FIFO from DSP EMIF B.

fifo_wr_en_n Out PCI write FIFO write enable, active low.

fifo_wr_paf_n In PCI write FIFO almost full, active low.

pci_rdfifo_blen_wr In PCI read FIFO burst length write. This is the write

enable to the interrupt burst counter control.

pci_rdfifo_blen[6:0] In The PCI read FIFO burst length count. This is used to

control the interrupt behavior so that once an interrupt is

signaled, it can only be reasserted after this number of

points are read.

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Cypress Semiconductor Perform CY7C1372D Betriebsanweisung Seite 89