Cypress Semiconductor Perform CY7C1372D Betriebsanweisung PDF herunterladen (Seite 39)

also. These are detailed in the software manual.

5.5 Debugging

It is inevitable that the logic will require some debugging and it is best to have a strategy for debug

before you actually use the hardware. Debugging on actual hardware is difficult because you have

poor visibility into the FPGA internals.

For HDL designs, the best and easiest debug method is simulation for functional and timing

problems. This gives the best visibility and interactivity to debug problems before the real

hardware is tested. A good set of test cases that stress the design should be run prior to working

on the real hardware. You will save time in the overall design process by doing a thorough job in

simulation. Sermon over.

There are several techniques that have worked for us on projects: Xilinx ChipScope, built-in test

modes, and judicious use of test points. Between these techniques and the capabilities of each

method, it is usually possible to find and fix bugs that are either functional design errors or timing

problems.

MATLAB Simulink developers can use the “hardware in the loop” features of system to debug the

design at a high level. Simulink can be used to generate test data or for viewing and analyzing

real hardware data. This is invaluable in debugging complex signal processing designs.

Here we will discuss a few of these techniques.

5.5.1 Built-in Test Modes

Another good way to debug your design is to have built-in test modes in the logic. If you plan

ahead for test, then you can more quickly validate your design later and spot problems. When you

finish the design, if the test generators and checkers can be left in the design, they are there later

as production debug or test.

In many designs, test pattern or data generators are invaluable since they provide known data into

the FPGA so that the output is known. If the data source is analog in the real design, substituting

perfect data is nice because it helps spot problems that may be hidden in the noise. The test

pattern may be an easily recognized stream, like incrementing numbers, that are easy to check in

the logic or on the test equipment. Also, its easier to test the extreme cases of the design that

may be difficult to reproduce with real signals.

Innovative Integration FrameWork Logic User Guide 39

Illustration 35: Typical Debug Block Diagram

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Cypress Semiconductor Perform CY7C1372D Betriebsanweisung Seite 39