Cypress Semiconductor Perform CY7C1372D Betriebsanweisung PDF herunterladen (Seite 77)

Port Direction Function

reset In Global reset for the component

d_clk In The system clock for the system interface.

d_ce In The system clock enable.

wren In Read enable for the application FIFO.

din In Data from the system to the internal FIFO.

fs In DAC sample rate clock

trigger In A/D trigger. When true, samples are stored in the

external FIFO.

af_thresh[9:0] In The fifo level at which the fifo_af signal will go

true.

fifo_af Out The internal FIFO is almost full when true.

fifo_count[9:0] Out The number of points in the internal FIFO,

synchronous to d_clk. Has 2 clocks of latency.

dac_underflow Out The DAC FIFO had an underflow error condition

when true. Once true, this underflow error flag

remains true until cleared. Multiple underflow

conditions could have occurred if the underflow

flag is true.

test In Test mode select. When true, an incrementing

count is substituted for the data for system test.

dac_d(13:0) In DAC data to the external FIFO.

dac_ext_fifo_wen_n Out Write enable to the external FIFO, active low. This

signal is true when the trigger is true.

dac_ext_fifo_ren_n Out Read enable to the external FIFO, active low. This

signal is true when data is moved from the

external FIFO to the internal FIFO.

dac_ext_fifo_reset_n Out Reset to the external FIFO, active low.

dac_ext_fifo_ae_n In External FIFO almost empty, active low. When

true the external FIFO has less then 511 samples

(when dac_fsel = “10”).

dac_ext_fifo_af_n In External FIFO input is amost full, active low.

When true, the external FIFO has less than 511

samples when dac_fsel = “10”.

dac_clk Out The DAC sample clock to the DAC and external

FIFO.

dac_ext_fifo_rclk Out External FIFO data read clock, equal to fs..

dac_ext_fifo_wclk Out External FIFO data write clock, equal to fs.

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Cypress Semiconductor Perform CY7C1372D Betriebsanweisung Seite 77