
As can be seen in the block diagram, the EMIF A is used as the primary interface to the analog
IO. The EMIF A memory space is decoded so that control and configuration registers are mapped
as well as burst FIFOs for the high speed data paths. EMIF B is used primarily as the PCI
interface bus, and travels through the Virtex2 en route to the Spartan2 logic. Two McBSP
interfaces are also provided.
6.1.4.1 Application Logic Help Files
An hyper linked help file system is available for Quixote logic developers. The
quixote_logic_help.zip file set available either on Innovative's web site or support CD provides a
navigable version of the logic files. This help system shows hierarchy, logic entities, important
processes and variables for the application design.
6.1.4.2 Memory Map
Memory mapped peripherals reside on both EMIFs in the Logic Framework that define the bus
interface type and timing parameters. A memory map for the Framework Logic is included below.
Most designers integrate application-specific features into the standard memory mapping to
preserve as much software as possible. Also, the memory decoding and data interface to the DSP
are architected in the logic to support the burst or asynchronous memory interfaces.
Innovative Integration FrameWork Logic User Guide 48
Illustration 44: Quixote Logic Block Diagram
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