Cypress Semiconductor Perform CY7C1372D Betriebsanweisung PDF herunterladen (Seite 47)

Function Tool Vendor Tool Name

Synthesis, Place and Route Xilinx ISE 7.1 or above

Simulation Mentor Graphics ModelSim 6.1

Bit and PROM Image Creation Xilinx Impact 7.1

Signal Processing Design MathWorks MatLAB 14 sp1

Logic Design Under MATLab Xilinx System Generator 7.1

Logic Debug and Testing Xilinx ChipScope 7.1

Logic JTAG Cable Xilinx Parallel Cable IV or others

Table 5: Logic Development Tools for Quixote

6.1.4 VHDL Application Logic Example

As a starting point, here is a big overview of what is attached to the Virtex 2 FPGA. All of the high

speed data interfaces have 32K sample FIFOs for buffering the data to the Virtex2 logic. The DSP

has both buses attached to the logic, and also two of the McBSP ports so that ample data

movement is supported.

The logic design is organized as a hardware interface layer, which provide the direct interface to

the external peripherals, and the application logic components that do specific functions for signal

processing and control. Hardware interface components in the design include the A/D interface

components, ii_quixote_adc, for example and the A/D interface, ad_interface, providing specific

triggering and data capture features in Quixote.

Innovative Integration FrameWork Logic User Guide 47

Illustration 43: Quixote Logic and Peripherals

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Cypress Semiconductor Perform CY7C1372D Betriebsanweisung Seite 47