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Port Direction Function

dsp_a_ofifo_rst[7:0] In Array of resets to the DSP input FIFOs.

dsp_a_ofifo_rd_count[7:0] Out Array of DSP output FIFO read counts. These are how

many points each DSP output FIFO has in it. This count

is 2 clocks latent and is synchronous to dsp_aeclk.

dsp_a_ofifo_wr_count[7:0

]

Out Array of DSP output FIFO write counts. These are how

many points each DSP output FIFO has in it. This count

is 2 clocks latent and is synchronous to d_clk.

Table 15: ii_quixote_emif_a Component Ports

MATLAB Simulink Component:

Ports on the MATLAB component have the same function as listed in the VHDL port list. Ports not

shown are connected in the top level design hardware interface layer.

Target Devices: Xilinx XC2V2000-4FF896C or XC2V6000-4FF1156

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Cypress Semiconductor Perform CY7C1372D Betriebsanweisung Seite 82