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the logic. This allows the best timing for getting the signal on-chip since the DSP has rather poor
setup timing. The decoding is all done using these registered bus control signals using clocked
processes for best timing control. Here is an example of the DSP write decode process:
write_gen: process (reset, dsp_aeclk, dsp_a_ea_q_s, dsp_a_ce_n_q, dsp_a_awe_n_q)
begin
if (reset = '1') then
dsp_a_wr(i) <= '0';
elsif (rising_edge(dsp_Aeclk)) then
if ((dsp_a_ea_q_s = CONV_STD_LOGIC_VECTOR(i,7)) and dsp_a_ce_n_q(0)='0' and
dsp_a_awe_n_q ='0') then
dsp_a_wr(i) <= '1';
else
dsp_a_wr(i) <= '0';
end if;
end if;
end process write_gen;
The registered addresses are dsp_a_ea_q_s and the registered control signals are dsp_a_ce_n_q
and dsp_a_awe_n_q. This example process generates the 128 DSP write signals that are output
from the DSP hardware interface component. If you modify the code, try to follow these examples
to avoid the timing problems associated with using the DSP signals directly into the chip.
Adding FIFOs to the Design
The DSP FIFOs are also in the ii_quixote_dsp_emif_a component including their decoding. We
have commented out some of the code but left it in the source for you to use if you need to add
another FIFO. Just change the generic num_fifos to the number you want (there will be an equal
number of input and output FIFOs) and the data readback process. In the readback process you
will need to modify the case statement to be
-- the data mux
-- here's how to decode multiple fifos
a_decode <= dsp_a_ce_n_q(1) & dsp_a_ea_q_s(22 downto 20);
--* the data is either the fifo or the async status registers
rdback: process (dsp_aeclk, dsp_a_ce_n_q(0))
begin
if (rising_edge(dsp_Aeclk)) then
case a_decode is
when “0000” => dsp_a_rdout <= X"00000000" & status_d;
when "0001" => dsp_a_rdout <= dsp_a_ofifo_dout(1);
when "0010" => dsp_a_rdout <= dsp_a_ofifo_dout(2);
when "0011" => dsp_a_rdout <= dsp_a_ofifo_dout(3);
when "0100" => dsp_a_rdout <= dsp_a_ofifo_dout(4);
when "0101" => dsp_a_rdout <= dsp_a_ofifo_dout(5);
when "0110" => dsp_a_rdout <= dsp_a_ofifo_dout(6);
when "0111" => dsp_a_rdout <= dsp_a_ofifo_dout(7);
when others => dsp_a_rdout <= dsp_a_ofifo_dout(0);
end case;
end if;
end process rdback;
Notice that the case has been changed to a_decodes from the original source. You may also
have to change the UCF file for the component area definition to fit all the new FIFOs in the area
Innovative Integration FrameWork Logic User Guide 58
- FrameWork Logic Users Guide 1
- 1 Table of Contents 2
- 2 List of Figures 4
- 3 List of Tables 6
- 4 Introduction 7
- 4.4 Where to Get Help 8
- 5 Logic Development Process 9
- Hardware Interface Layer 10
- Application 11
- (your logic does here) 11
- 5.1.2 VHDL Simulation 12
- 5.2.1 Installation 20
- 5.2.2 MATLAB Simulink Use 22
- SRAM used 24
- 5.4 Loading Logic 27
- 5.4.1 JTAG 27
- 5.4.2.2 Velocia Download 38
- 5.5 Debugging 39
- 5.5.1 Built-in Test Modes 39
- 5.5.2 Xilinx ChipScope 40
- CAUTION: 41
- 6 FrameWork Designs 46
- 6.1.4.2 Memory Map 48
- R/W CE Type 49
- 6.1.4.3 Clocks 51
- 6.1.4.3.1 Clock Sources 52
- 6.1.4.3.2 Domains 53
- 6.1.4.4 A/D Interface 53
- 6.1.4.5 DAC Interface 54
- 6.1.4.6 DSP Interface 55
- 6.1.4.6.1 DSP Bus EMIF A 55
- 6.1.4.6.2 DSP Bus EMIF B 59
- 6.1.4.7 Event Log 59
- 6.1.6 Synthesis and Fitting 60
- 6.1.6.2 Constraints 61
- 6.1.6.2.1 Timing Constraints 61
- 6.1.6.3 Logic Utilization 63
- 6.1.7 Place and Route 66
- 6.1.8 Simulation 68
- 6.1.8.3 Simulation notes 70
- 6.1.9.1 Loading over PCI 70
- 6.1.9.2 Loading over JTAG 70
- 6.2 PMC UWB 71
- 6.2.1 Overview 71
- 6.2.2 Target Devices 71
- 6.2.3 Development Tools 71
- 6.2.4 Application Example 71
- 7 Framework Library 72
- 7.1.1.1 ii_quixote_adc 73
- MATLAB Simulink Component: 75
- 7.1.1.2 ii_quixote_dac 76
- Supported Platforms: Quixote 79
- Description: 79
- Port Direction Function 81
- Target Devices: any 84
- MATLAB Simulink Components: 86
- Target Devices : any 90
- Target Device : Any 94
- 8 Generic Components 95
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