Cypress Semiconductor Perform CY7C1372D Betriebsanweisung PDF herunterladen (Seite 55)

The data flows to the DAC from the external FIFO under control of the triggering logic. The

hardware interface component takes data from the DSP FIFO unstacks it from 64-bit words, error

corrects it, and puts the data into the external FIFO. The unstacker unpacks four data samples,

two for each DAC from the 64-bit word.

If you need to modify the DAC signal chain to add signal processing, the best place is usually

before the A/D hardware component. This allows you to use the FIFO in the DAC hardware

component as a clock domain transition element and also allows you to directly put DAC data into

the output FIFO. The DSP or some signal processing logic can be the source of the data.

The DAC hardware interface component simply takes a trigger input and plays data when true.

The uber_trigger_dac component supports many of the common types of triggering and produces

a trigger signal indicating when data is to be played. Most applications use one of the many

trigger modes or need something similar. Triggering modes include play a number of points, play

for a length of time, and play when triggered by the DSP or external source. If you have a simple

triggering method, you may just put your own in that is less complex.

6.1.4.6 DSP Interface

6.1.4.6.1 DSP Bus EMIF A

The DSP interface uses the ii_quixote_dsp_emif_a hardware interface component as the primary

interface between the DSP EMIF A, the 64-bit bus, and the application logic. This includes the

high data paths to the DACs and from the A/Ds, and the slower control and status registers.

Innovative Integration FrameWork Logic User Guide 55

Illustration 47: Quixote DAC Interface Block Diagram

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Cypress Semiconductor Perform CY7C1372D Betriebsanweisung Seite 55