defined for the ii_quixote_dsp_emif_a component.
6.1.4.6.2 DSP Bus EMIF B
The EMIF B interface in the Framework Logic is primarily used as a pass-through to the PCI
FIFOs. Data flowing to the PCI streaming engine in the Spartan2 logic passes through the Virtex2
with simple registers in the data path to improve timing. A test register has been implemented to
allow the DSP to verify its connection to the Virtex2 during test.
As can be seen from the memory map, two CE spaces on the the EMIF B interface are open for
use in the Framework Logic if the streaming engine interface is used. Interface methods similar to
those used on EMIF A should be used since the bus is 100 MHz.
6.1.4.7 Event Log
The Alert Log component provides a means to monitor important events in the hardware for
monitoring and control of the hardware. Alerts give a message to the DSP that details the event
that occurred, when it occurred and in some cases a system status relevant to that alert. The
alerts are commonly used to monitor the time line of data acquisition processes by recording
when the start and stop triggers occurred, error conditions on the FIFOs, and input over-range
conditions.
The hardware manual details the specific alerts monitored in the Quixote Framework Logic
design. They include start and stop triggers, out-of-range and user input for example. By
generating an alert from these inputs, the application software can record the time each of these
important events occurred.
Quixote implements a 20 MHz timebase that is used as the system time. The time stamp
component just keeps a 32-bit counter driven by this 20 MHz clock to record when each alert
occurred. It is reset by a DSP controlled bit in the logic. Other clocks or external inputs may be
used for time stamping by providing the time stamp with that clock. This allows the alert to be
used for external sample clocks to count samples which is useful in some applications.
In your custom application logic, the alert log can be used to monitor the occurrence of other
important events by connecting the alert log input to the signal to be monitored. The rising edge of
the input signal is used to generate an event, so it may be necessary to make logic to generate a
rising edge from your input. These inputs are sampled by the alert log system clock and must be
true a minimum of 2 system clocks wide to be recognized.
Note: The alert log was previously called the event log. To be compatible with software
terminology, it has been changed to alert log since event is a special word to DSP software.
References to the Event Log are identical to Alert Log.
6.1.5 MATLAB Simulink Logic Examples
There are several examples using Simulink that illustrate use with Quixote. The logic
components are used within the quixote_intf.vhd top logic file. In a normal installation, the
example files are located at C:\MATLAB7\toolbox\xilinx\sysgen\examples\Quixote_Examples .
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