
Port Direction Function
reset In Global reset for the component
d_clk In The system clock for the system interface.
d_ce In The system clock enable.
rden In Read enable for the application FIFO.
dout Out Data from the internal FIFO to the system.
dvalid Out Data valid, synchronous to d_clk, indicates that
data is valid when true.
fs In A/D sample rate clock
trigger In A/D trigger. When true, samples are stored in the
external FIFO.
test In Test mode select. When true, an incrementing
count is substituted for the data for system test.
fifo_ae Out The internal FIFO is almost empty when true.
adc_ovr In ADC overrange bit. When true, the ADC detected
an overrange on the sample. This bit is appended
to each sample as bit 15 into the external FIFO.
adc_d(13:0) In ADC data from the external FIFO.
adc_ext_fifo_wen_n Out Write enable to the external FIFO, active low. This
signal is true when the trigger is true.
adc_ext_fifo_ren_n Out Read enable to the external FIFO, active low. This
signal is true when data is moved from the
external FIFO to the internal FIFO.
adc_ext_fifo_reset_n Out Reset to the external FIFO, active low.
adc_ext_fifo_ae_n In External FIFO almost empty, active low. When
true the external FIFO has less then 511 samples
(when adc_fsel = “10”).
adc_ext_fifo_ir_n In External FIFO input is ready, active low. When
true, there is room in the external FIFO for more
samples to be collected.
adc_clk_p
adc_clk_n
Out The A/D sample clock output differential pair.
Signal standard is PECL.
adc_ext_fifo_rclk Out External FIFO data read clock, equal to fs..
adc_ext_fifo_wclk Out External FIFO data write clock, equal to fs.
adc_ext_fifo_fsel(1:0) Out External FIFO flag select. See table below.
adc_ext_fifo_ld Out External FIFO load. Sets FIFO flag levels
according to table below. See TI SN74V283
datasheet for complete details.
Table 12ii_quixote_adc Component Ports
Innovative Integration FrameWork Logic User Guide 74
Kommentare zu diesen Handbüchern