Cypress Semiconductor Perform CY7C1372D Betriebsanweisung PDF herunterladen (Seite 4)

2 List of Figures

Illustration Index

Illustration 1: VHDL Development Process...................................................................... 10

Illustration 2: Logic Architecture Showing Hardware and Application Layers.................11

Illustration 3: Compiling the Simulation Libraries............................................................13

Illustration 4: Setting Simulation Library Compilation Properties.................................... 13

Illustration 5: Invoking ModelSim from Xilinx ISE..........................................................14

Illustration 6: Configuring Xilinx ISE to use a custom DO file........................................ 15

Illustration 7: Loading the simulation in ModelSim..........................................................16

Illustration 8: Example ModelSim Workspace After Loading.......................................... 17

Illustration 9: ModelSim Wave Window Example............................................................18

Illustration 10: MATLAB Simulink Development ...........................................................19

Illustration 11: MATLAB Directory.................................................................................. 20

Illustration 12: Executing the MATLAB installation command........................................20

Illustration 13: Matlab Installation Directory Example..................................................... 21

Illustration 14: Simulink Product Library Example...........................................................21

Illustration 15: Building a Simulink Project...................................................................... 22

Illustration 16: Example use of MATLAB Gateways........................................................23

Illustration 17: Example of Real-time Signal Capture in MATLAB.................................24

Illustration 18: Example of Real-time Arbitrary Wave Generation in MATLAB.............24

Illustration 19: Xilinx Implementation Tools.................................................................... 25

Illustration 20: Xilinx System Generator Implementation Control....................................26

Illustration 21: Getting Started with IMPACT.................................................................. 28

Illustration 22: Choosing the Operation Mode for IMPACT.............................................28

Illustration 23: Choosing the Boundary Scan Mode for IMPACT.................................... 29

Illustration 24: Automatic JTAG Chain Detection using IMPACT.................................. 29

Illustration 25: Selecting the Configuration Image Using IMPACT................................. 30

Illustration 26: Programming Devices using JTAG under IMPACT.................................31

Illustration 27: Using IMPACT to Make a PROM Image................................................. 32

Illustration 28: Selecting the PROM Operating Mode in IMPACT.................................. 32

Illustration 29: Selecting the Configuration Method in IMPACT..................................... 33

Illustration 30: Selecting the PROM size in IMPACT...................................................... 34

Illustration 31: Selecting the BIT file in IMPACT............................................................ 35

Illustration 32: Ready to Make the PROM Image in IMPACT......................................... 36

Illustration 33: Successful PROM Image Generation Using IMPACT............................. 36

Illustration 34: Velocia Logic and DSP Software Download Applet................................ 38

Illustration 35: Typical Debug Block Diagram..................................................................39

Illustration 36: Debugging with ChipScope.......................................................................40

Illustration 37: Xilinx Parallel IV Cable for Debug and Development............................. 41

Illustration 38: Xilinx Parallel Cable IV Target Cable...................................................... 41

Illustration 39: Xilinx Parallel Cable IV Pinout on IDC 5x2 2MM Header...................... 41

Innovative Integration FrameWork Logic User Guide 4

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Cypress Semiconductor Perform CY7C1372D Betriebsanweisung Seite 4