Cypress Semiconductor Perform CY7C1372D Betriebsanweisung PDF herunterladen (Seite 2)

1 Table of Contents

Table of Contents

1 Table of Contents.............................................................................................................2

2 List of Figures.................................................................................................................. 4

3 List of Tables.................................................................................................................. 6

4 Introduction......................................................................................................................7

4.1 Prerequisite Experience and Required Tools........................................................... 7

4.2 Organization of this Manual.....................................................................................8

4.3 Logic Component Naming Conventions..................................................................8

4.4 Where to Get Help....................................................................................................8

5 Logic Development Process.............................................................................................9

5.1 Developing Using VHDL.........................................................................................9

5.1.1 Using the FrameWork Library in VHDL.......................................................11

5.1.2 VHDL Simulation......................................................................................... 12

5.2 Logic Development using MATLAB Simulink..................................................... 19

5.2.1 Installation...................................................................................................... 20

5.2.2 MATLAB Simulink Use................................................................................ 22

5.2.3 Using Simulink in High Speed Applications..................................................23

5.3 Making the Physical Logic.....................................................................................25

5.3.1 Place and Route Reports.................................................................................26

5.4 Loading Logic ....................................................................................................... 27

5.4.1 JTAG.............................................................................................................. 27

5.4.2 Loading the Logic Using PROM Images........................................................31

5.4.2.1 Making the Device Image.......................................................................31

5.4.2.2 Velocia Download.................................................................................. 38

5.5 Debugging.............................................................................................................. 39

5.5.1 Built-in Test Modes........................................................................................39

5.5.2 Xilinx ChipScope.......................................................................................... 40

5.5.2.1 Declaration Of ChipScope Core in VHDL............................................. 42

5.5.3 Debugging in MATLAB Simulink.................................................................45

6 FrameWork Designs...................................................................................................... 46

6.1 Quixote...................................................................................................................46

6.1.1 Overview........................................................................................................ 46

6.1.2 Target Devices................................................................................................46

6.1.3 Development Tools........................................................................................ 46

6.1.4 VHDL Application Logic Example................................................................47

6.1.4.1 Application Logic Help Files..................................................................48

6.1.4.2 Memory Map.......................................................................................... 48

6.1.4.3 Clocks..................................................................................................... 51

6.1.4.3.1 Clock Sources................................................................................. 52

6.1.4.3.2 Domains...............................................................................................53

6.1.4.4 A/D Interface.......................................................................................... 53

6.1.4.5 DAC Interface.........................................................................................54

Innovative Integration FrameWork Logic User Guide 2

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