Cypress Semiconductor Perform CY7C1372D Betriebsanweisung Seite 50

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Seitenansicht 49
CE
Space
Address (Hex) Description Logic
Device
R/W CE Type
Configuration
0x80140000 A/D Stop Trigger Selection Virtex2 W Async
0x80160000 A/D Stop Trigger Configuration Virtex2 W Async
0x80180000 A/D Trigger Threshold Virtex2 W Async
0x801A0000 A/D Threshold Channel
Enable
Virtex2 W Async
0x801C0000 A/D Frame Timer
Configuration
Virtex2 W Async
0x801E0000 A/D Frame Count
Configuration
Virtex2 W Async
0x80200000 D/A Start Trigger Selection Virtex2 W Async
0x80220000 D/A Start Trigger
Configuration
Virtex2 W Async
0x80240000 D/A Stop Trigger Selection Virtex2 W Async
0x80260000 D/A Stop Trigger Configuration Virtex2 W Async
0x80280000 Not used - - -
0x802A0000 Not used - - -
0x802C0000 D/A frame timer Configuration Virtex2 W Async
0x802E0000 D/A Frame Counter
Configuration
Virtex2 W Async
0x80300000 UD configuration Virtex2 W Async
0x80320000 Analog Configuration Register Virtex2 W Async
0x80340000 Analog Compare DAC Virtex2 W Async
0x80360000 Not used - - -
0x80380000 SBSRAM 0 Address Virtex2 W Async
0x803A0000 SBSRAM 1 Address Virtex2 W Async
0x803C0000 Not used - - -
0x803E0000 A/D Gain Memory Virtex2 W Async
0x80400000 A/D Offset Memory Virtex2 W Async
0x80420000 D/A Gain Memory Virtex2 W Async
0x80440000 D/A Offset Memory Virtex2 W Async
0x80460000 Not used - - -
0x80480000 Not used - - -
0x804A0000 Not used - - -
0x804C0000 PCI FIFO burst read length Virtex2 W Async
0x804E0000 PCI FIFO burst write length Virtex2 W Async
0x80500000 UD Data Virtex2 R/W Async
Innovative Integration FrameWork Logic User Guide 50
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