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FrameWork Logic Users GuideInnovative IntegrationCopyright 2005. All rights reserved. All information in this document is property of Innovative Int

The application development begins with the FrameWork Logic code for the product you are using. In many cases, the example application code provides

Code for your application layer design can be created in a number of ways: written in VHDL or Verilog, created in MATLAB, or included as a black box n

5.1.2 VHDL SimulationSimulation is an important part of the logic development process. All designs that are targeted at using the large logic devic

Simulation can be started in either the Xilinx ISE environment, or by using the ModelSim tool in a standalone mode. In Xilinx ISE, select the test be

When you enter the ModelSim tool from Xilinx ISE, it will execute a default macro that compiles the files and begins the simulation. If you enter in

Innovative Integration FrameWork Logic User Guide 15 Illustration 6: Configuring X

When the design is loading, you will see each components loaded in the transaction window as shown here. If anything fails to load, check that its por

Once the design is loaded, the design hierarchy is shown in the Workspace window with the test bench at the top of the hierarchy. Here is an example.

Once you are inside the ModelSim environment, you should be able to use the tools to run simulations of the design. The wave window is many times the

5.2 Logic Development using MATLAB SimulinkMATLab Simulink provides a powerful method of developing logic using a high level design tool that integra

1 Table of ContentsTable of Contents 1 Table of Contents...

5.2.1 InstallationYou must have installed MATLAB Simulink prior to installing the product MATLAB support. The co-simulation library is provided as a

4. Quit MATLAB and restart..Now the product library should be visible in the Simulink Library Browser window.The library is now ready for use in MATLA

5.2.2 MATLAB Simulink UseIn MATLAB, you can make new block diagrams for logic designs using the libraries for Xilinx and the specific product. Creat

An important feature in the Simulink environment is the ability to use Simulink for active co-simulation. This means that real hardware can be access

To get signals from MATLAB into the hardware, the SRAM can be used as an arbitrary waveform generator when it is loaded with a test waveform that is

5.3 Making the Physical LogicAfter the logic has been created, either with HDL or MATLAB, it must be implemented in the logic through a process of pl

process. Double-clicking the icon allows you to configure the Xilinx ISE tools that are used for the logic build just as you would for an HDL design.

File extensionContents What to Look For.BLD The output from the NGDBuild process that link all the logic togetherThere should be no errors. This prog

The Xilinx IMPACT application is used to load the logic into the application FPGA. The IMPACT tool may be invoked from the Xilinx ISE tool or as a sta

The next screen will prompt for what type of configuration to perform. Choose the Boundary Scan Mode as shown.Next, IMPACT will prompt for the JTAG c

6.1.4.6 DSP Interface...55 6.1.4.6.1 DSP Bus EMIF A...

If all goes well, IMPACT will find all the devices in the JTAG chain and display them as shown in this example. If not, check the cable connection to

5.4.2 Loading the Logic Using PROM Images 5.4.2.1 Making the Device ImageFor all Innovative products, an EXORMacs format (.EXO) text file must be ge

The next screen will prompt you to either configure devices or make a configuration file. To make a PROM image, select Prepare Configuration Files.In

For a generic PROM file, used for most Innovative products, on the next screen you should select PROM file for the image type.The PROM properties must

In PROM Configuration screen, select the following options:• Select Parallel PROM.• Select EXO as File Format.• Memory Fill Value - 0xFFthen provide a

You will then be prompted before the file is made – you last chance to not overwrite you last PROM if you did not change the name or file path. Innova

The final screen will report successful operation. Innovative Integration FrameWork Logic User Guide

You are now ready to load the PROM image using one of the tools provided by Innovative or by your application. Each family of cards has a specific log

5.4.2.2 Velocia DownloadThe Velocia family of products, including Quixote and Quadia, use a simple Windows application to download logic images to th

also. These are detailed in the software manual. 5.5 DebuggingIt is inevitable that the logic will require some debugging and it is best to have a st

2 List of FiguresIllustration IndexIllustration 1: VHDL Development Process... 10I

Another built-in test method is to use data checkers in the logic sprinkled through the data chain help to spot the source of problems. If you have a

to pre-trigger or post-trigger in the software which makes trigger design easier.Here is one of the common cables used for debug, just for reference.

5.5.2.1 Declaration Of ChipScope Core in VHDLThe ChipScope core is simple to use. Just connect up the signal for observation to the data ports, the t

Here is its instantiation during a debug session.Innovative Integration FrameWork Logic User Guide

Innovative Integration FrameWork Logic User Guide 44 ---------------------------

In this case, the designer was using the DSP EMIF A clock as the ChipScope core clock and had several triggers including DSP memory decodes and softwa

6 FrameWork Designs 6.1 Quixote 6.1.1 OverviewThe Quixote has two FPGAs on it : a Xilinx Spartan2 (200K gates) and a Xilinx Virtex2 (2M or 6M gates).

Function Tool Vendor Tool NameSynthesis, Place and Route Xilinx ISE 7.1 or aboveSimulation Mentor Graphics ModelSim 6.1 Bit and PROM Image Creation Xi

As can be seen in the block diagram, the EMIF A is used as the primary interface to the analog IO. The EMIF A memory space is decoded so that control

CE SpaceAddress (Hex) Description Logic DeviceR/W CE TypeBCE0 0x60000000 PCI FIFO Spartan2 R/W BurstBCE1 0x64010000 Readback Register (for test) Spar

Illustration 40: ChipScope Core Declarations... 43Illustration 41: ChipScope Core Inst

CE SpaceAddress (Hex) Description Logic DeviceR/W CE TypeConfiguration0x80140000 A/D Stop Trigger Selection Virtex2 W Async0x80160000 A/D Stop Trigger

CE SpaceAddress (Hex) Description Logic DeviceR/W CE Type0x80520000 SBSRAM 0 Data Virtex2 R/W Async0x80540000 SBSRAM 1 Data Virtex2 R/W Async0x8056000

6.1.4.3.1 Clock SourcesThere are several clocks available to the designer in the logic that are intended for different functions as shown in the foll

The clocks buffering, phase lock components and distribution is controlled in the ii_quixote_clocks component in the logic. The system clock, commonl

The data flows from the A/D into the external FIFO under control of the triggering logic. The hardware interface component receives the data from the

The data flows to the DAC from the external FIFO under control of the triggering logic. The hardware interface component takes data from the DSP FIFO

The Quixote EMIF A memory decodings are arranged so that ACE0 is asynchronous and ACE1 is synchronous burst memory. Generally speaking, the async peri

needed. Normally, this is set by the DMA channel.Since there are very few timing adjustments in the DSP EMIF control for sync registers, logic designe

the logic. This allows the best timing for getting the signal on-chip since the DSP has rather poor setup timing. The decoding is all done using the

defined for the ii_quixote_dsp_emif_a component. 6.1.4.6.2 DSP Bus EMIF BThe EMIF B interface in the Framework Logic is primarily used as a pass-throu

3 List of TablesIndex of TablesTable 1: Document Revision History...

File name (.mdl) Contentsdownsample Illustrates the use of the A/D, DAC and SRAM components to make a loop in the logic from A/D to DAC and includes s

6.1.6.2 ConstraintsThere are several important classes of constraints used by the Framework Logic : timing, pin placement and IO standards. These con

NET "beclkout1" TNM_NET = "beclkout1";NET "aeclkout1" TNM_NET = "aeclkout1";As can be seen, EMIF A clock (aecl

There are several constraints internal for the DCM and Block RAMs such as INST "inst_clocks/Inst_aclk_dcm/dcm_inst" LOC = "DCM_X1Y0&qu

Innovative Integration FrameWork Logic User Guide 64 Design Information-----------

Note that the map report file shows that the 2M device for example uses 57% of the slices, but 42% of the flip-flops so the logic is loosely packed.

6.1.7 Place and RouteThe Xilinx tools report the result of the place and route process in the PAR report. This PAR report shows the timing results f

Innovative Integration FrameWork Logic User Guide 67 -----------------------------

The extract of the PAR report shown here is for the 6M device. Notice that the timing constraints are compared to the actual timing achieved. If you

6.1.8.2 Simulation Models for QuixoteThere are several models used in the Quixote simulations for system level testing.Model Filename Functional Beha

4 IntroductionThis manual is written to assist in the creation, implementation and testing of custom logic for Innovative Integration products. The s

6.1.8.3 Simulation notesDuring simulation, you may want to reduce the DCM reset time period to reduce simulation time. The actual hardware requires a

6.2 PMC UWB 6.2.1 Overview 6.2.2 Target Devices 6.2.3 Development Tools 6.2.4 Application ExampleInnovative Integration

7 Framework Library 7.1 Hardware Components 7.1.1 Quixote Hardware ComponentsInnovative Integration FrameWo

7.1.1.1 ii_quixote_adcSupported Platforms: QuixoteDescription: This component is an interface between the Quixote application logic and the A/D and i

Port Direction Functionreset In Global reset for the componentd_clk In The system clock for the system interface.d_ce In The system clock enable.rden

The external FIFO is TI SN74V283, or equivalent. The programable flags are set as shown in this table. For more details, consult the TI datasheet.MA

7.1.1.2 ii_quixote_dacSupported Platforms: QuixoteDescription: This component is an interface between the Quixote application logic and the DAC an

Port Direction Functionreset In Global reset for the componentd_clk In The system clock for the system interface.d_ce In The system clock enable.wren

Port Direction Functiondac_ext_fifo_fsel(1:0) Out External FIFO flag select. See table below.dac_ext_fifo_ld Out External FIFO load. Sets FIFO flag

7.1.1.3 ii_quixote_dsp_emif_aSupported Platforms: QuixoteDescription: This component is the DSP External Memory InterFace (EMIF) A bus interface. It

Logic development and are discussed in this manual. If you are using other tools, they should have similar capabilities. 4.2 Organization of this Ma

Innovative Integration FrameWork Logic User Guide 80 Illustration 61: ii_quixote_e

Port Direction Functionreset In Global reset for the componentd_clk In The system clock for the system interface.d_ce In System clock enable. fs In S

Port Direction Functiondsp_a_ofifo_rst[7:0] In Array of resets to the DSP input FIFOs.dsp_a_ofifo_rd_count[7:0] Out Array of DSP output FIFO read cou

7.1.1.4 ii_quixote_dioSupported Platforms: QuixoteDescription: This component is a simple digital IO port used on Quixote that has an input register

Port Direction Functionreset In Global reset for the componentd_clk In The system clock for the system interface.d_ce In System clock enable. din[31:

7.1.1.5 ii_quixote_sbsramSupported Platforms: QuixoteDescription: This component provides an interface from the application logic to synchronous burs

Port Direction FunctionAddr[19:0] Out SBSRAM address bitslbo_n Out SBSRAM burst mode; 0= linear (only mode supported)Sclk Out 2x clock to SRAMCke_n Ou

These two components are used to provide the interface to the Quxiote SRAM under Simulink. The Quixote SBSRAM 0 component is the hardware interface,

7.1.1.6 ii_quixote_dsp_emif_bSupported Platforms: QuixoteDescription: This component is the interface between the Quixote application logic DSP EM

Port Direction FunctionReset In System reset.ref_clk In Reference clock. On Quxiote this is a 10 Mhz clock.bm_reset In Bus master reset bit. Resets

5 Logic Development ProcessThe FrameWork Logic system supports two logic development methods: VHDL, or MATLab Simulink, or a combination. Each syste

Port Direction Functionfifo_rd_d[15:0] In Data bus to the PCI write FIFO from DSP EMIF B.fifo_rd_en_n Out PCI read FIFO write enable, active low.fifo_

7.1.1.7 ii_quixote_clocksSupported Platforms: QuixoteDescription: This component provides the clocks for the application logic and external devices.

Port Direction FunctionReset In System reset.dsp_aeclk_i In DSP EMIF A clock input.dsp_beclk_i In DSP EMIF B clock input.ref_clk_i In Reference clock

7.1.1.8 ii_quxiote_pmc_j4Supported Platforms: QuixoteDescription: This component is a simple port for the PMC J4 connections that is easily customiz

Port Direction FunctionReset In System reset.clk In Clock inputce In Clock enable; unusedDin[31:0] In Data bus inputpmc_j4_wr In PMC J4 output registe

8 Generic Components 8.1 ii_event_logSupported Platforms: QuixoteDescription: The event log component is to provide a mechanism for recording the chr

Innovative Integration FrameWork Logic User Guide 96 Illustration 65: ii_event_log

Port Direction Functionclk In Clock inputce In Clock enable; unusedref_clk In Reference clock for time stampingreset In Master reset. Clears all pend